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Timing analysis on partitioned design in Cadence SOC Encounter

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anwei7208

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After assemble the partitions, I tried to do static timing analysis over the whole design, but it the timing report shows 0 delays in the buffers of clock paths. It seems that the tool didn't consider the wire load while computing timing. In the timing analysis of each individual partition, however, the path delays looked fine. Can anyone tell me why and how to fix? Did I miss something after assemble the partitions? Thanks very much.
 

assembleDesign care about only physical information. Please set analysis Mode, loadTimingCon after assembleDesign .
 

Hi, could it be that you have not propagated your clocks for STA? Are they still IDEAL from an STA stand point?
 

Thank you guys for the replies. I guess it's because the top level clock tree is still in ideal status. I'll look into it.
 

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