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What is the best OPAMP topology?

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extremis

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I would like to design an OPAMP using 0.6μm technology with the following specifications:

Vdd=3V (single)
Av>80dB
GB>20MHz
ICMR=0.5-2.5V
output swing: 0.5-2.5V
phase margin: >50deg
settling time (0.1%): 20ns (2pf load)
PSRR: >40dB

What is the simplest topology that would meet these requirements?


Thank you in advance.
 
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I'd try a folded-cascode topology with gain boosting or, if the output swing is not enough, remove the gain-boosting and add one common-source output driver.
 
Thanks for the advice. I am afraid that a folded cascode topology would not satisfy either the upper or the lower ICMR requirement (Vt,n=0.7V, Vt,p=-0.9V).
 

why dont u try a rail-to-rail architecture. The only point the seems difficult to achieve otherwise are you ICMR and OR.

Its amazing you have access to such an old process though..
 

use a folded cascode topology while you use two folded input stages for n and p, that is you need two tails and two differential input pairs
 

Indeed. In my last job I used mostly processes which are
older than most of the posters here, and are still running
in production.

Not every job needs, or can be done by ever-smaller
transistors. Sometimes a bigger hammer is just the ticket.
 

Me too. I use 0.8um more than anything and still quote jobs in 1um or larger. It is all about the most cost effective solution for my customers.

Keith
 

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