65nm CMOS with Multi-finger problem in HSPICE simulation

Hello everyone,

I am doing a simulation to draw the current (Ion) curve of a pmos transistor with different numbers of fingers for a certain width. The currents should decrease when more fingers are applied. while in my simulation result, the current is increasing following the increment of the number of fingers.

The code is shown below:
********************************************************************
SPICE test of power gating 65nm

.LIB 'lib/st065/LPmos_bsim4_hvt.lib' hvtlp_tt
.LIB 'lib/st065/common_poly_cd.lib' pro_tt
.LIB 'lib/st065/common_active_cd.lib' pro_tt
.LIB 'lib/st065/common_go1.lib' pro_tt
.LIB 'lib/st065/common_poly_res.lib' pro_tt
.LIB 'lib/st065/common_active_res.lib' pro_tt
.LIB 'lib/st065/diodeiso.lib' diodeiso_typ
.LIB 'lib/st065/mismatch.lib' mismatch_no

.global vdd 0 vss
.param vs=1.0
.param vd=0.99

.param def_w=100
.param def_l=0.09


**** Voltage sources ****
V1 psource gnd 'vs'
V2 pdrain gnd 'vd'

**** Test circuit ****
.TEMP 125

**simulation for Ion, Vds = 10mv
xpmos1 pdrain gnd psource psource phvtlp w = 100 l = 'def_l' nfing = 'finger'

** Default Simulation - Type, Resolution & Duration
.TRAN 10PS 100NS sweep finger 10 200 10

.meas tran Ion avg I(V2) from=10ns to=20ns

.END
******************************************************************

The subckt of this low power high vth pmos and the most important parameters are shown below
******************************************************************
.subckt phvtlp d g s b
+ w = 0.12
+ l = 0.06
+ nfing = 1
+ tometer = 1e-06
+ mult = 1

.param wm = 'w*tometer'
.param lm = 'l*tometer'

M1 d g s b phvtlp w='wm/nfing'
+ l=lm
+ m='mult*nfing'
+ nf=1
......
.ends
*****************************************************************

Are there any bugs in this netlist? or the current should increase following the increment of finger numbers for 65nm high vth cmos?
Thanks

jy00349890 said:

I am doing a simulation to draw the current (Ion) curve of a pmos transistor with different numbers of fingers for a certain width.

Click to expand...

Actually your netlist doesn't produce different numbers of fingers for a certain width, but different numbers m='mult*nfing' of transistors with w='wm/nfing', i.e. you get m parallel transistors.

jy00349890 said:

The currents should decrease when more fingers are applied. while in my simulation result, the current is increasing following the increment of the number of fingers.

Click to expand...

Due to paralleling, the series resistances decrease, hence the current increases.

jy00349890 said:

... or the current should increase following the increment of finger numbers for 65nm high vth cmos?

Click to expand...

Yes, because you don't increase the no. of fingers, but the multiplicity m. This behaviour is independent of the process.

erikl said:

jy00349890 said:

I am doing a simulation to draw the current (Ion) curve of a pmos transistor with different numbers of fingers for a certain width.

Click to expand...

Actually your netlist doesn't produce different numbers of fingers for a certain width, but different numbers m='mult*nfing' of transistors with w='wm/nfing', i.e. you get m parallel transistors.

jy00349890 said:

... or the current should increase following the increment of finger numbers for 65nm high vth cmos?

Click to expand...

Yes, because you don't increase the no. of fingers, but the multiplicity m. This behaviour is independent of the process.

Click to expand...

Thanks erikl, do you know how to change the fingers for this pmos device in this case?

Added after 2 hours 51 minutes:

I read the BSIM model manul and found that the it seems the nf is for multi-finger configuration. Do I need to change the width when I change the number of fingers (nf)?
e.g. if I want to implemet a pmos with the width of 100um and the fingers of 10. is the expression below correct?
xpmos1 pdrain gnd psource psource phvtlp w = 100 l = 'def_l' nf = 10

jy00349890 said:

... I read the BSIM model manual and found that it seems the nf is for multi-finger configuration. Do I need to change the width when I change the number of fingers (nf)?

Click to expand...

Yes, I think so: total_w = finger_w * nf

jy00349890 said:

e.g. if I want to implemet a pmos with the width of 100um and the fingers of 10. is the expression below correct?
xpmos1 pdrain gnd psource psource phvtlp w = 100 l = 'def_l' nf = 10

Click to expand...

I think you must write: ... w = '100/nf' l = 'def_l' nf = 10

Hi There,
I'm using Hspice for simulating a circuit in which there are pmos and nmos transistor with 500000um and 300000um width respectively. I have been trying to use multiplier(m) and fingure(nf) to shorten these transistors.Unfortunately I have got a problem with NF. And I don't know how I can solve it. I use 0.18um CMOS technology. Could you possibly help me?
I look forward to hearing from you.
Best Wishes,
Ebi

Re: circuit simulation with very large transistor width

For pre-layout simulation, you can directly use w=500000

For layout, use e.g.

The extractor should create a correct post-layout netlist.

Re: circuit simulation with very large transistor width

Hi erikl,
I knew what you mentioned.However It's not worked. I don't know why!!! What shall I do?

Re: circuit simulation with very large transistor width

eahmadi said:

However It's not worked. I don't know why!!! What shall I do?

Click to expand...

How should I know, if you don't even reveal what you did, and what the error message was?

Re: circuit simulation with very large transistor width

I'm really grateful for spending your time to help me.
I have a complicated code which I can realize what It is. I use code like this as below in Hspice:

mP d1 g1 s1 s1 pch3 l=0.3u w=100u m=100 nf=50
mN d1 g2 gnd gnd nch3 l=0.35u w=100u m=100 nf=30

I simulate my code with this transistor. I want to have multiplier and finger at the same time so I use Like above.
As I simulated this code, it did not work!!!
Could you let me know your opinion?
Thanks

- - - Updated - - -

And it's too confusing that there isn't any error in "Edit LL" reporting file. I don't know why!!!

HSPICE doesn't know the parameter nf. Did you check if your pch3 and nch3 models know both parameters m & nf? If not, you have to use w=500000 (resp. w=300000). In pre-layout simulation this shouldn't make any difference.

For post-layout simulation, the foundry-provided extractor runset (extract rules) should correctly extract the numbers m and nf corresponding to your layout, and arrange for inserting the corresponding m transistors and their nf-involved parasitics into the post-layout (extracted) netlist.

Thanks for your explanation
Unfortunately, I haven't been checking if pch3 and nch3 models can support m and nf. could you tell me how I can check them?

eahmadi said:

Unfortunately, I haven't been checking if pch3 and nch3 models can support m and nf. could you tell me how I can check them?

Click to expand...

By reading their model files.

Hi There,
I have a question about TSMC 0.18um technology. Could you possibly tell me How I can find the variation of voltage range for NMOS and PMOS transistor? For example, which range can NMOS and PMOS work properly?
Thanks in advance
Ebi

Hi everyone,
I'm working with Hspice.I have faced with warning mentioned in below when I use pulse source:


**warning** dc voltage reset to initial transient source value
in source 0:vmp new dc= 0.1800D+01

Could you possibly tell me how I can solve it?
Thanks in advance,
Ebi

Pulse source used as DC source

eahmadi said:

... I use pulse source:

**warning** dc voltage reset to initial transient source value
in source 0:vmp new dc= 0.1800D+01

Could you possibly tell me how I can solve it?

Click to expand...

You don't need to solve it, this is just a notification that - in a DC analysis - your pulse source is used with its initial voltage (1.8V in this case) as a DC voltage source.
#####################################################################
BTW: please don't hijack threads with different titles. Because of the different title you won't get a good chance to receive a reply on your own question - apart from this I think it's not fair in the face of the original thread starter. Better start your own thread with a good descriptive title!

Re: Pulse source used as DC source

Hi Erikl,
Thanks for notification. Sorry I'm a newcomer and I'm not familiar with creating new topic. Ok, I will try to make a specific topic.
Best Regards,
Ebi