Problems with PECL interface LVDS by AC coupling

I have a circuit like the attached diagram for interfacing PECL(3.3V) to LVDS by AC coupling.
I have draw all signal levels at each input/output pin.

The problems are:
1) The negative input of LVDS receiver DS90LV110 has the same pulse as positive input; those two pulses are in phase. I am wondering where the pulse on negative come from?
2) The output of MC100EP01 doesn’t have proper DC offset. What is wrong with it?

Thank you for your answers.

PECL interface LVDS

Your first problem is the MC100EP01 doesn't have a /Q output. That may be because you haven't terminated it correctly, as far as I can see. The termination resistors should go to Vcc-2V and should be 50 ohms. If you are running off 5V then you need to terminate to 3V.

Keith.

PECL interface LVDS

Hi,
Sorry Keith, I can not agree in all points, than if you have an ECL gate you can use it as PECL (Positive ECL) too, as its Vee will be on GND, Vcc on +3.3V---+5.5V in practicum, as its writen on the data sheet too.
In such modus is a termination_better: emitter pull downs_OK to GND.
Btw: you must not think only in 50 Ohms for that!
They can be some value up to some KOhms & down to tenth of Ohms (only output transistors current limit & dissipation is to check), max with KOhms it will deliver nice slow edges because the parasite/stray capacitances...For 2-3 nsec edge times is common to use 220-330 Ohms.
If EP01 Q has proper function on these termination, than why is it not OK for Q* pls?
@hg81
I think, EP01 has some other problem,seems me that the 150 Ohm is not present on Q*.
I would check it to first alone-take the couple C`s to LV110 out....
At these high-speed ECLs is very important to have pro IC a 10+ 100nF & nearest on the VCC/VEE pins!!
Because has these LVDS line Receiver practically an RRInput, why can you not take the simplest DC coupling refer pls to data sheet, page8?
Good luck!
K.

PECL interface LVDS

Karesz,

My interpretation of the data sheet is that even for PECL the outputs should be terminated to VCC-2V see note 12 below table 9.

I agree you don't necessarily need to terminate with 50 ohms.

Keith

PECL interface LVDS

Yes Keith,
I know, but these is only for lower_or minimal possible_ dissipating!
Its otherwise NOT A MUST, than the internal I source/parts are referenced to Vee too_ yet=GND!... Its otherwise practicable (for a conventional 5V ECL), than so can you direct connect to GND terminated 50 Equipments as oscilloscope, SA...
K.

Re: PECL interface LVDS

The shown waveforms are not plausible. Either the ECL device is defective or the real circuit is not corresponding to the schematic. Of course we can't see what's wrong from a distance.

You don't show a timescale, but it looks like you're operating the circuit at low frequencies, where the AC coupling can't work. A DC coupling would be easy, as karesz mentioned. For low and medium speed, it's no problem to overdrive the LVDS input. If you are intending real ECL/LVDS speed, you should attenuate the signal to specified LVDS input levels. Impedance matching isn't an issue as long as both devices are near to each other

In any case, you should care to get a correct differential ECL output first.
.

PECL interface LVDS

Yes, I mean too_
1,
is the Q* output transistor killed or
2,
is hes pull down not present on it...

PECL interface LVDS

A short circuit between pins 5 and 6 is a possibility.

Keith

Re: PECL interface LVDS

I found out the problem finally.

they bought MC100EP23 instead MC100EP01.

PECL interface LVDS


Interesting_gratulation!
K.

Re: PECL interface LVDS

Thank you all too