Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

What is a 'gate coupling' from semicon design point of view?

Status
Not open for further replies.
D

dog2mari

Newbie level 4
Joined
Jun 13, 2010
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Seoul Korea
Activity points
1,326
my question is what a 'gate coupling is" and how it is related to GIDL?

ASAP please... please
 

Re: What is a 'gate coupling' from semicon design point of v

GIDL: Gate Induced Drain Leakage.

GIDL currents arises in the high electric field under the gate/drain overlap region. GIDL occurs at a low gate voltage Vg and high drain Voltage Vd and generates carriers into the substrate and drain from surface traps.

(taken from: Kaushik Roy :"Low Power CMOS VLSI Circuit Design")
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top