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Rise time of a line...

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Pheetuz

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I am currently doing a serial transmission project in VHDL. The problem i am having is that the data change / data read from one chip to another respectivly occur on a common clock pulse ... I need to make the data read occur a fraction of a second later, of the exact time I am not sure ... Basically, I was thinking that if i used a capacitor on the clock line then it would increase the time taken for the logic level to rise to a level that the reciever would recognise as a 1 ... Therefore making the read time a fraction of a second later????

Any ideas???

Thanks.

/Pete
 

Hi,
your delay capacitance will be more effectfull if you will apply a serial restor befor the C.
Also, its a R-C or lowpass filter (too) and time constant is to calculate as a "normal" time constant with T=R*C......
K.
 

"a fraction of a second" seems a correct timescale for mechanical relay circuits. Digital logic possibly needs a few 10 ns of delay (of course a nanosecond is also a fraction of a second...).
 

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