yoran
Newbie level 2
Hey,
I have a question about Verilog. I have a bunch of wires h_in[016*640)-1] as an input in a module. They represent 640 values of 16 bits. I want to store those into registers, so
I tried to make this more generic using a for-loop and generate for-loop but I couldn't succeed. How can I write this using a loop statement?
Thanks,
Yoran
I have a question about Verilog. I have a bunch of wires h_in[016*640)-1] as an input in a module. They represent 640 values of 16 bits. I want to store those into registers, so
Code:
reg signed [0:16-1] h[0:639];
h[0] <= h_in[0*16:(0+1)*16-1];
h[1] <= h_in[1*16:(1+1)*16-1];
h[2] <= h_in[2*16:(2+1)*16-1];
h[3] <= h_in[3*16:(3+1)*16-1];
h[4] <= h_in[4*16:(4+1)*16-1];
...
h[638] <= h_in[638*16:(638+1)*16-1];
h[639] <= h_in[639*16:(639+1)*16-1];
I tried to make this more generic using a for-loop and generate for-loop but I couldn't succeed. How can I write this using a loop statement?
Thanks,
Yoran