matlab code for software radio reciever

• Apr 28, 2004

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wentao_m.pdf

Who have experience in implementing a digital receiver (DDC) in FPGA?
I'm searching books/documents/ etc. etc. about it?
Can anyone help me?
Thanks in advance.

 

• Apr 29, 2004

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Usman Hai

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digital receiver pakistan

I m currently working on same DDC for Software defined radios using FPGA.
www.altera.com/products/ip/dsp/m-alt-ref_dsp_stratix_ddc.html
check this link it will help u to start.

have u done any work on it.

Usman hai
PAKISTAN

 

• Apr 29, 2004

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Usman Hai

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pakistani digital resiever rates

check this doc.
USMAN HAI

 

• Apr 30, 2004

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BGA

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Re: DIGITAL RECEIVER

Do you have documentation on Al*era DDC Reference Design?

 

• Apr 30, 2004

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ddt694

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DIGITAL RECEIVER

a digital receiver includes many parts, such as downconvert, decimation filter, match filter, AGC, timing recovery device, carrier recovery device, FEC decoder, equalizer, etc.
DDC may be the simplest part. in general, it is only
two or four multipliers(complex multipliers).

 

• Apr 30, 2004

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BGA

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Re: DIGITAL RECEIVER

For digital receiver I mean downconverter and decimation filter... any help/documentation?

 

• Apr 30, 2004

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dainis

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Re: DIGITAL RECEIVER

h**p://www.engr.usask.ca/dept/ele/thesis/wentao_m.pdf
h**p://scholar.lib.vt.edu/theses/available/etd-101299-012534/unrestricted/thesis1.pdf
h**p://scholar.lib.vt.edu/theses/available/etd-08312000-15590002/unrestricted/jcd4_thesis.pdf

 

• Apr 30, 2004

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Usman Hai

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Re: DIGITAL RECEIVER

You shud make a plan.Take individual blocks and then merge them into one unit.
1-NCO
2-Mixer
3-low pass filter
4-downsampling
5-decimation filters.

USMAN HAI
PAKISTAN

 

• Aug 1, 2004

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Re: DIGITAL RECEIVER

Hi

A good IP Core for DDCs are available from xilinix in ISE.

Regards

 

• Dec 27, 2004

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Re: DIGITAL RECEIVER

Hi

Can anyone say how many DDC can be implemented in single FPGA such as Virtex-II?

Regards

 

• Dec 28, 2004

• #11

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ye.hui

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Re: DIGITAL RECEIVER

Circuit_seller said:

Hi

Can anyone say how many DDC can be implemented in single FPGA such as Virtex-II?

Regards

Click to expand...

it depends on what the DDC is used for. for example, the DDC in WCDMA with multi-channel is larger than in many other applications.

 

• Dec 28, 2004

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Circuit_seller

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Re: DIGITAL RECEIVER

Hi

I need an DDC with fixed decimation ratio of about 30 and 32-bit NCO accuracy.

Regards

 

• Dec 30, 2004

• #13

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ye.hui

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Re: DIGITAL RECEIVER

i think you can try it in ISE. the DDC you described is not large.

 

• Dec 30, 2004

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Re: DIGITAL RECEIVER

Hi again,

My input sampling rate also is less than 10MHz, can i utilize a high speed FPGA to implement more DDCs on a single FPGA?

Regards

 

• Jan 13, 2005

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LOSTINCITY

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DIGITAL RECEIVER

in my work i needed to deal with a signal with code rate of 125Mbps , can this work on digital receiver?

 

• Jan 22, 2005

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Re: DIGITAL RECEIVER

Hi guys,

For architectural idea's it might be usefull to look at the datasheets of currently available Digital Down Converter IC's form Analog Devices. They give in most cases a lot of nice design details which might help you te set up your own design.
Have a look at the AD6620 at the analog website.

Regards

 

• Nov 29, 2009

• #17

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Re: DIGITAL RECEIVER

64 channel DDCs can implemented in a single FPGA such as VirtexII Pro30