Cluny
Junior Member level 1
Hi,
I've been designing a class-ab latch comparator. This comparator hast to compare a minimal differential input signals of 1mV with the speed of at least 100 MHz. The common problems occurring with latch comparators like offset-voltage, kickback-noise and so on... are not a problem.
Unfortunately after doing a mismatch Monte-Carlo-Sim only 10% work correctly. It seems that the latch is very sensitive. So I increased the transistor-length of the most critical tranisistor-pair in my circuit to reduce the relative error of mismatch. But otherwise increasing the length leads to a time-problem. This means the simulation fails now due to the high frequency. Ok, I tried to reduce the load-capacitance to become more comfortable with the time... but I have still a low yield.
I hope that you could see my problem in reaching a high yield, which is absolutely necessary for me. It's quite frustrating.
Someone an idea that helps?
Thanks
I've been designing a class-ab latch comparator. This comparator hast to compare a minimal differential input signals of 1mV with the speed of at least 100 MHz. The common problems occurring with latch comparators like offset-voltage, kickback-noise and so on... are not a problem.
Unfortunately after doing a mismatch Monte-Carlo-Sim only 10% work correctly. It seems that the latch is very sensitive. So I increased the transistor-length of the most critical tranisistor-pair in my circuit to reduce the relative error of mismatch. But otherwise increasing the length leads to a time-problem. This means the simulation fails now due to the high frequency. Ok, I tried to reduce the load-capacitance to become more comfortable with the time... but I have still a low yield.
I hope that you could see my problem in reaching a high yield, which is absolutely necessary for me. It's quite frustrating.
Someone an idea that helps?
Thanks