Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Interconnect Cap Verification of Cadence Layout with CST MWS

Status
Not open for further replies.
E

emreamrzohny

Newbie level 1
Joined
Jan 10, 2010
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,288
Does anyone know how to import a Cadence GDSII/dxf file into CST Microwave Studio to perform a verification of the interconnect capacitance.

I don't trust the results of Assura and I would like to verify the results with a 3D EM simulator.

Should I draw everything again by hand or is there a way to directly import the extracted design ? ( If not CST MWS then Momentum or Sonnet ? )
 


Re: Interconnect Cap Verification of Cadence Layout with CST

Manjunatha_hv said:
Even it directly interfaces to Cadence Virtuoso...
Click to expand...

Here's a description of the design flow for Sonnet within the Cadence RFIC environment:

**broken link removed**

See page 15 ff for a design flow overview with some screenshots.

For interconnect/lines, you might want to use the RLCG model (called "mtline" in Spectre). On page 43 ff, there is a description hot to get create that output data.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top