Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

ADC/DAC Driver Settling Time Requirements

Status
Not open for further replies.
H

hsharghi

Newbie level 4
Joined
May 11, 2006
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,317
Hi,

I'm designing an op amp to buffer the output of a 12-bit 1 MSPS DAC. My question is how fast should the op amp settle to meet the requirements of less than 1/4 LSB? The output load of the amplifier is 10 KOhm || 100 pF.

I am having trouble finding the formula to compute this. Your response would be greatly appreciated.

Thanks!
 

The settling time depends partly on the OP higher order gain poles, resepctively the closed loop gain phase margin. In so far, there's
no simple formula. Referring to an explicite settling time specification in the OP data sheet would be the most simple way, a lot
of high speed OPs have it. You'll also need to care for isolation of the capacitive load, e.g. by a series resistor, otherwise all settling
time calculations may be dwarted.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top