doubt about simulation using TSMC cmosp18.5.2 (Resistor)

Hi All,

I am trying to simulate a resistor (poly resistor) using using TSMC cmosp18.5.2.
I have already included the models (rf018.scc, cor_res.scs, etc).
However, when I change the section, for example, tt_res to ss_res, anything happens with the resistor.
That is... changing the model, the resistor performance doesnt change.
Can anyone help in this topic?

Thanks in advance.

Try looking at the resistor models and see if they are different. ss is presumably slow N, slow P - maybe it doesn't actually change the poly resistors.

Keith

Edit: I have just had a look at some TSMC models (not necessarily the same ones as yours) and I can see no evidence of ss affecting the resistors.

Hi Keith! Thanks again for you help. (Always you)

I agree with you. Section `ss, tt, ff, sf, fs` does not affect the resistor.
But what I changed was the resistor model. Note that I replaced `tt_res` to `ss_res`. (I have checked this sections in the resistor models)

The point is that I need to do a corners simulation & Monte Carlo analysis including resistors. But I don't know which model I can use for this.
There are some models that seems to affect the resistor performance, but they didnt change anything.

Do you know which model should I use?
(I know that this question is generic... ) but maybe you have same insight.

Thanks again,

The problem with ss ff sf fs etc models is that they move verything in synchronisation. You need Monte Carlo models. I don't use Cadence, I use an Hspice compatible simulator, and often fabs don't include Monte Carlo models for anything other than Cadence. So I often have to create my own models from process data.

Looking through some TSMC 0.18um data I found this: "The model for this technology has added the capability for mismatch analysis of an identical and closely spaced resistor pair. Random variations in Gaussian distribution of the total resistance are included in the model to account for the mismatch performance. The designers will need to turn off (mismatchflag=0) or turn on (mismatchflag=1) in the macro model for nominal or Monte-Carlo analysis" which implies there is a Monte Carlo model, but I must admit I haven't found one. It may be that I am not looking in the right place or that it is only in the Cadence models and they aren't straight text so I cannot read them.

Sorry I cannot be more help. Maybe a Cadence/TSMC expert will chip in. You could ask TSMC where they have hidden the MC models! I once had to ask a fab where the protection diode was because I couldn't find the model - it was in the resistor library!

Keith.

Thanks very much Keith!
I have already read all the manuals provided by foundry, and I didnt find anything important. I think that the Design kit manual from TSMC is poor in information when compared with other fondries (for instance, IBM, AMS)...
So, thanks again.. I will continue to search.

Best Regards,

Palmeiras

Are you using Cadence?

Keith.

Added after 3 minutes:

Just found this on one of the pdfs:

The mismatch models are with subcircuit names "xxx_mis" with a suffix "mis".

Not sure if it helps, but try searching for anything with "mis" in it.

Keith.

Added after 1 minutes:

Found some models called "rnpo1_mis" in the library files I have for 0.18um.

Keith.

Hi Keith,

Yes... I am using Cadence Tools.
Thanks for your attention.
I didnt find anything relevant... But I will double check.
I would like to simulate the BGR over process variation.
Do you have experience in designing trimming circuits? (for instance, trimmable resistor).
I know that fuse links is widely used. And I also know that in my case
laser cutting is not possible (I will not have access to this).

Based on your experience, could you say how to design a trimmable resistor?
Any tips regarding this issue is very important to me.
I will create a topic for this.

Thanks very much.

Palmeiras

Dalton,

Try searching for the text "_mis" in your model files. Hopefully you will find the correct one.

I haven't done a lot of trimming. One process I use has "zener zapping". This has the advantage that it is an "anti-fuse" so doesn't splatter metal everywhere when you blow it. They also have a cell with serial programming logic so you can do lots of zeners with out needing dozens of pins. It is process specific though, I guess.

I have only used fusing once, on a bipolar process. I am no expert with it, but as I understand, the concern with doing it on packaged parts is the metal has to go somewhere but is effectively trapped in the package and so can migrate back to where it came from. Fusing at the wafer stage is better, but makes a mess of the test area with metal dust. The other issue is whether to leave holes in the passivation above the fuse to give somewhere for the metal to go. The advice from the foundry in this case was that it should blow a hole in the passivation. That seemed to be correct. It made a very clean hole. The fuse was simply a deliberate narrow portion of the metal with the metal routing being very wide. The dimensions were 20um & 2.4um, I seem to think. For the trimming I simply had a string of different value resistors. Depending on the error we could blow the appropriate fuses to trim. By making the resistor values a "binary code" we could get quite precise trimming with just a few connections - e.g. 16 values from 4 fuses.

Maybe someone like erikl may have some wider experience on trimming - it might deserve a new thread.

Keith.

Hi Keith,

I am thankful for your information. This option zener zapping seems to be great; but I don't think I have this feature in TSMC.
I didnt know about this problem of dust. So, based on your explanation, the method is not reliable. am I right?

But in your design, have you inject the current through pins or using pad (glasses holes)?

Palmeiras

Fusing is reliable, but there are potential issues if it is packaged when you do the fusing. My information is second hand though. Fusing at wafer level is fine, but (again, second hand information) the test people don't like it because of the aluminium dust. There is actually a picture of the fuse structure on my web site, taken from a chip I blew the fuses of without passivation holes, I used normal pads for blowing but you could use 'test pads' which are smaller and don't have to be at the peripherary.

The zener zapping is on some of Xfab's processes.

Creating your trimming depends a bit on you resistor values. You want to try to keep good matching for nostrils of it using multiples of a 'unit' resistor and then either add series or parallel ones to adjust it. Series makes more sense - with parallel the values would have to be quite high.

Keith

Hi Keith,

Thanks again for all your help.
I created a new topic with this question, to receive more feedbacks.
I added a figure describing the way I plan to do my trimmable resistor.
(A very simple scheme)
Could you take a look and give your opinion?
Maybe you can see something strange.
I would connect each bit signal to external pin.



Best wishes,