Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Problem with adding SSRAM to FPGA as pin is not assigned

Status
Not open for further replies.

doraemon

Super Moderator
Staff member
Joined
Jun 21, 2009
Messages
1,256
Helped
292
Reputation
592
Reaction score
303
Trophy points
1,363
Location
Japan
Activity points
12,961
Hello everybody!

I am an absolute beginner in this field, but I would like to use FPGA.
I bought (well, my boss did) a NEEK (NIOS embedded evaluation kit)
which implements a Cyclone III device.

I am using the latest tools (Qartus 9.1 sp1, and NIOS IDE 9.1).

In order to understand the basics, I first built a led blinking program.

1. In SOPC builder, I have added a NIOS processor, internal RAM
(32k), a 4-bit PIO and a JTAG interface.

2. In NIOS IDE, I have built a 10 lines basic program to flash the
leds. It works. As the memory is very small, I would like to add
an interface to the external SSRAM and use the SSRAM as the execution
RAM.

3. I have added SSRAM in SOPC builder. Then as there was an error
message, I have also added an Avallon MM tristate bridge.
After pin assignment, I compiled.
There is a critical warning remaining: one pin is not assigned.
This pin is the sram clock. The schematics say that the ssram clock
is connected to FPGA's pin A2.

So my question is simple: how do I route the system clock to pin A2?
Is it possible to do it inside of SOPC builder?
Is it necessary to edit verilog files (if yes, which one?)

Thanks,

Dora
 

Adding SSRAM to FPGA

Dora,
The way I have done this before is by creating a top level HDL module to encapsulate the SOPC builder project. That way you can add other logic on the outside of the SOPC project if you desire and you can do things like route the SSRAM clock. You could also create the module in SOPC builder to route the clock out, but this may be more work.
 

Re: Adding SSRAM to FPGA

Hello!

Thanks for your reply!
Could you develop a little bit? I'm an absolute beginner, so I have no idea
about how to "encapsulate" an object. And I have also no idea on how to create
a module in SOPC builder.

By the way, as I get a lot of trouble for starting, here are **broken link removed**, in the
hope it will help somebody else.
Tutorial 1 works fine. Tutorial 2 is on its way if I could solve that problem.
By the way, I will also add other types of memory, an SD card interface, etc,
step by step.

Any remarks on the technical contents or on tips to improve my english would
be welcome.


Dora
 

Adding SSRAM to FPGA

Actually, have you looked at the example projects that come with the NEEK? I know some of these will use the built in SSRAM. Specifically I have used the projects for the uCLinux distribution. You should be able to look at how the SSRAM clock is connected in these projects and figure out how to apply it in your design.
 

Re: Adding SSRAM to FPGA

Hello!

Thanks for your reply!

Yes, I hav had a look at the examples.
There are many examples, but they are not appropriate for me. I am an
absolute beginner, so befpre learning how to make an image viewer or
whatever other example, I have to learn and understand first how to connect
a simple processor to a simple RAM. In the examples, the clock to the
SSRAM is made using a PLL. I want first to try with a simple "wire", a plain
connection from the clock input (PIN_A9) to the ssram clock output (PIN_A2).

Dora
 

Adding SSRAM to FPGA

I am thinking that you are going to want to use the PLL output clock to connect the SSRAM. Since the CPU is most likely being clocked off the PLL clock you are going to want them to be in the same clock domain.

Otherwise you have to create a wrapper type module and then instantiate the result of the SOPC project. Then simply just do an assign statement for the input to output. So you will find the HDL instantiation template that is generated by SOPC builder. Create a new top level file. Instantiate the top level module. Then add whatever I/Os you want.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top