Hello everybody!
I am an absolute beginner in this field, but I would like to use FPGA.
I bought (well, my boss did) a NEEK (NIOS embedded evaluation kit)
which implements a Cyclone III device.
I am using the latest tools (Qartus 9.1 sp1, and NIOS IDE 9.1).
In order to understand the basics, I first built a led blinking program.
1. In SOPC builder, I have added a NIOS processor, internal RAM
(32k), a 4-bit PIO and a JTAG interface.
2. In NIOS IDE, I have built a 10 lines basic program to flash the
leds. It works. As the memory is very small, I would like to add
an interface to the external SSRAM and use the SSRAM as the execution
RAM.
3. I have added SSRAM in SOPC builder. Then as there was an error
message, I have also added an Avallon MM tristate bridge.
After pin assignment, I compiled.
There is a critical warning remaining: one pin is not assigned.
This pin is the sram clock. The schematics say that the ssram clock
is connected to FPGA's pin A2.
So my question is simple: how do I route the system clock to pin A2?
Is it possible to do it inside of SOPC builder?
Is it necessary to edit verilog files (if yes, which one?)
Thanks,
Dora
I am an absolute beginner in this field, but I would like to use FPGA.
I bought (well, my boss did) a NEEK (NIOS embedded evaluation kit)
which implements a Cyclone III device.
I am using the latest tools (Qartus 9.1 sp1, and NIOS IDE 9.1).
In order to understand the basics, I first built a led blinking program.
1. In SOPC builder, I have added a NIOS processor, internal RAM
(32k), a 4-bit PIO and a JTAG interface.
2. In NIOS IDE, I have built a 10 lines basic program to flash the
leds. It works. As the memory is very small, I would like to add
an interface to the external SSRAM and use the SSRAM as the execution
RAM.
3. I have added SSRAM in SOPC builder. Then as there was an error
message, I have also added an Avallon MM tristate bridge.
After pin assignment, I compiled.
There is a critical warning remaining: one pin is not assigned.
This pin is the sram clock. The schematics say that the ssram clock
is connected to FPGA's pin A2.
So my question is simple: how do I route the system clock to pin A2?
Is it possible to do it inside of SOPC builder?
Is it necessary to edit verilog files (if yes, which one?)
Thanks,
Dora