rakesh045
Newbie level 6
I am in need of a vhdl code which divides a 24 bit numerator by a 24 bit denominator.
The denominator is always greater than or equal to numerator.
So the value will always be between 0 and 1 and I require upto 3 decimal places
The numerator and denominator are both std_logic_vectors
Is is possible to represent the signal in fixed point arithmetic and still get the result.
pls help me... its urgent...
The denominator is always greater than or equal to numerator.
So the value will always be between 0 and 1 and I require upto 3 decimal places
The numerator and denominator are both std_logic_vectors
Is is possible to represent the signal in fixed point arithmetic and still get the result.
pls help me... its urgent...