Mamdouh
Member level 1
hi when i link the artisan dual sram to my design using synopsys design compiler and report_timing i found that the path to the output port QB inherit a delay of 999ns which certainly violates the setup time the question is why this massive delay!!!!!!!!!!!!!!
note : i use Artisan dual SRAM compiler tsmc90nm
plzzzzzzzz i need a quick reply coz i need to deliver the design with zero violations by the next Friday
note : i use Artisan dual SRAM compiler tsmc90nm
plzzzzzzzz i need a quick reply coz i need to deliver the design with zero violations by the next Friday