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a proplem with artisan dual sram compiler

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Mamdouh

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hi when i link the artisan dual sram to my design using synopsys design compiler and report_timing i found that the path to the output port QB inherit a delay of 999ns which certainly violates the setup time the question is why this massive delay!!!!!!!!!!!!!! :cry:

note : i use Artisan dual SRAM compiler tsmc90nm

plzzzzzzzz i need a quick reply coz i need to deliver the design with zero violations by the next Friday
 

i got the same problem, anyone who can help me?
 

well if you look at the *.lib you see the timing parameters are 999. you can try to use set fault path or something in the design compiler
 

well if you look at the *.lib you see the timing parameters are 999. you can try to use set fault path or something in the design compiler

Yes, The first stage you need to do is go and see the memory *.lib. While I'm not suggested to set flase path on memory Q output, becase usually this is a real timing path need constrained.

For the 999ns delay, you memory must have a input port named like "EMA", "EMAA" or "EMAB". You have to go to the memory DOC to see the usage of these inputs, then you will get the idea.

To fix this problem, you can use "set_case_analysis" and set the DC enviroment "case_analysis_with_logic_constants" to true. //here maybe some typing error

Thanks.
 
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    ee171

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Hi yx.yang,

Many thanks for helping. Could you please explain on the settings for DC? Only need to check on those two options you mentioned? I think I missed use those EM[AB] ports; tied them all to 3'b000. I have been stuck on this part for the last few days as well :)
 

Hi yx.yang,

Many thanks for helping. Could you please explain on the settings for DC? Only need to check on those two options you mentioned? I think I missed use those EM[AB] ports; tied them all to 3'b000. I have been stuck on this part for the last few days as well :)

Hi, ee171:
I think you must have located where the problem is. How to fix the problem is your job.
Thanks.
 

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