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Deadzone design for the phase detector

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YCLO

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Does anyone have the idea of designing the deadzone of phase/frequency detector? What do ppl usually be aware of while designing the deadzone and what's the typical value of deadzone (in ps) we may have in 2 ~ 5 GHz frequency synthesizer?

Thank you!
 

yes..I know this may sound weird but I need this one too. I'm having a DLL right now. As I tested the complete loop. I found out that the input frequency and the feedback (from my 4 stage current starved delay line) has this ~500ps phase difference always. With this, the PD keeps on producing UP signal which always charging the capacitor and never discharge since no DOWN comes out. As a result, the Vcontrol+ goes to Vdd and the Vcontrol- goes to ground, and I believe my DLL will never lock.....
 

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