Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
i think you know that setup and hold time is the period on both side of active clock edge where input should be stable...
practical use of it is that... if your data is not stable at clock edge route clock such a way that it reaches ff or register when data is in stable condition and or similarly you can route data...
this is the simplest practical aspect of these two defination
The answer to your question simply is that setup and hold times determines the maximun frequency of operation for your design (if we neglect clock skew).
As you know, a D-flip flop is the most important element in digital design. We also know that data flow can be synchronous, asynchronus or by consensus. If your application works as a synchronous system, you must be sure that data will move betwen succesive stages. If you neglect setup and hold times, then you may use a frequency of operation greater than the maximum allowable frequency. So, you may lose bits resulting in errors.
I just like providing an example, try to make a simple design with pipelined adder that consists of two adders, one of them is located at the bottom left of the fpga and the other is located at the top right of the FPGA chip and a register in between them . Read the timing report carefully and decrease the "diameter" between the two adders. This example will give you the feeling how important is setup and hold times.
I hope I added something to your knowledge about clock managenent.
Then dont look at FF (say D-FF) from top level. go inside
D-FF is made of 2 latches, infact a master-slave latch. read how a latch works ? check whether the basic assumption of a latch is giving output exactly when the enable signal is active or the output is obtained after some delay(actual scenario !!).
now whatever you learnt about latch needs to be propogated to top level to reach a FF.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
