Re: How to include header file in VHDL module
There's no header file option in VHDL. To make project wide assignments of constants and define types or functions, you can use a package.
All packages are compiled to the library work by default.
to include the package in a compilation unit
package DEFS is
CONSTANT MAJOR_VERSION: INTEGER := 0;
CONSTANT MINOR_VERSION: INTEGER := 22;
CONSTANT MAXREG: integer := 52;
TYPE REGS_TYPE is array (0 to MAXREG) of STD_LOGIC_VECTOR(15 downto 0);
FUNCTION opndrn(inp: std_logic) return std_logic;
end package DEFS;
package body DEFS is
FUNCTION opndrn(inp: std_logic) return std_logic IS
CASE INP is
WHEN '0' => return '0';
WHEN OTHERS => return 'Z';
end package body DEFS;
As an interesting feature, the types defined in a package can be referenced in an entity port definition.
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