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  1. #1
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    How to include header file in VHDL module

    Hi all,


    Could you tell me how to include a header (.h) file in VHDL.
    In verilog we does like this.

    entity X
    end entity;

    `include "rtl/def_HarrisCorner.h"

    How it will achieved in VHDL module. And where exactly it will be done the VHDL file.
    Any help is appreciated.

    Regards

    •   Alt6th February 2010, 15:06

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  2. #2
    FvM
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    Re: How to include header file in VHDL module

    There's no header file option in VHDL. To make project wide assignments of constants and define types or functions, you can use a package.

    All packages are compiled to the library work by default.

    Code:
    package DEFS is
      CONSTANT MAJOR_VERSION: INTEGER := 0;
      CONSTANT MINOR_VERSION: INTEGER := 22;
      CONSTANT MAXREG: integer := 52;
      TYPE REGS_TYPE is array (0 to MAXREG) of STD_LOGIC_VECTOR(15 downto 0);
      FUNCTION opndrn(inp: std_logic) return std_logic;
    end package DEFS;
    
    package body DEFS is
    FUNCTION opndrn(inp: std_logic) return std_logic IS
     begin
        CASE INP is
          WHEN '0' => return '0';
          WHEN OTHERS => return 'Z';
        END CASE;	
     end;
    end package body DEFS;
    to include the package in a compilation unit
    Code:
    LIBRARY work;
    USE work.defs.all;
    As an interesting feature, the types defined in a package can be referenced in an entity port definition.


    1 members found this post helpful.

    •   Alt6th February 2010, 16:31

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  3. #3
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    Re: How to include header file in VHDL module

    Hi,

    Thanks for answer. Its working!

    Regards,



    •   Alt7th February 2010, 05:40

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  4. #4
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    Re: How to include header file in VHDL module

    Hi all,


    Thanks for your responses.

    Added after 1 hours 13 minutes:

    Hi all,

    If there are more no of constants in def file, can I keep them in seperate file and include. If so how???

    Anybody could help me.

    Regards



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