Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Protection of VHDL and/or AHDL codes

Status
Not open for further replies.
S

sir-yuri

Newbie level 3
Joined
Oct 31, 2003
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
18
Can I add some instruction or option to define specific FPGA (CPLD)device in my project. My Customer is given 'edif' or 'tdo' files for further sinthesis. I do not want him to implement another device except specified one for compilation. How to protect my design?
8O
 

I donot know, but I have a idea, I remember that Xilinx FPGA can access its JTAG logic from internal logic, if you can do that, you can access the special JTAG ID of the FPGA, it indicates what type of part it is. so you can lock it!! just my thoughts, hope you can get it
 

I am not very sure if you can access JTAG logic from inside, check it yourself. if it is good, let me know, maybe I will do it next time
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top