Not another flip flop question

Hi all,

I read lot about latches and flip flops. Came to the conclusion that flip flops are edge triggered and latches are level tirggered.

Can someone tell me how this edge triggering actually happens?

I know how it works in a master-slave flip flop and this requires two edges one(rising or falling) for the master to pass input to the slave and the next immediate one (falling or rising) for the slave to pass the input to output. This is what happens in ICs like 7473: Master Slave JK flip flop and from the datasheet : The logic states of the J and K inputs must not be allowed to change while the clock is HIGH.

Ok fine till now.

Now come to a D flip flop: 7474. It doesn't say anything about master slave architecture and from datasheet: The data on the D input maybe changed while the clock is low or high without affecting the outputs as long as the data setup and hold times are not violated.
and the flip flops are positive edge triggered.

So 7474 requires only one edge and is an edge triggered device but 7473 requires 2 edges( one rising and one falling) and is also an edge triggered device.

Now can someone please tell me how 7474 works with only one edge and what actually happens during this setup and hold time?

See a functional circuit from the TI 74HC74 datasheet

Hi FvM,

Thanks for the reply. So it shows that D flip flops are implemented using transmission gates. Similarly are there other flip flops too using this architecture?
Can you provide some part numbers?

Thanks in advance.

Transmission gates are only availiable in CMOS designs. TTL devices can be expected to use an equivalent gate circuit.
You should be able to figure it out. The interesting point is, that the designs implements a master-slave principle,
I would expect other flip flops to do the same.