Deterministic Finite Automata using Verilog/VHDL

Hi all,

I want to implement a simple DFA on FPGA using Verilog or VHDL. I read from some papers that the states of the DFA and the state transition table can be stored in BRAM. Anybody here can give me a hint how to do this? Thank you.

erman_wellem said:

Hi all,

I want to implement a simple DFA on FPGA using Verilog or VHDL. I read from some papers that the states of the DFA and the state transition table can be stored in BRAM. Anybody here can give me a hint how to do this? Thank you.

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Hi, I'm new to this board.

I've mostly developed for ASICs. I'm somewhat new to FPGAs. While it's ultimately true that state transition information can be stored in BRAM.

I usually reserve such an explicit setup for state machine "engines", where there is a host of actions the engine could take. And a host of data paths through the engine such that a particular path is setup, based on the action the engine needs to perform.

Once the engine knows the action it wants to execute, it would retrieve the proper bit codes from a BRAM to set the engine's datapaths and go.

Is that really what you want to do or are you looking for something simpler?

In the simpler sense, BRAMs might get used implicitly (behind the scenes) by the synthesis / place & route tools to store the final result of your compile run. In this simpler case, the actual low level details of BRAM resource utilization are hidden from you. Also, in this case, all you need to focus on is the "case/when" coding of your state machine (DFA).

Here's a link to the coding of a DFA (state machine), for you (in the simpler case)...
**broken link removed**

Hope this helps.

Thank you. I will try to take a look at the link you give...