omara007
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Hi folks
I am trying to map my vhdl coded memory into Xilinx distributed RAM .. I'm using Xilinx Spartan-3A DSP chip (XC3SD1800A-4fg676) and Xilinx ISE 11.3.
I'm facing 2 problem:
1. Synthesis using XST is taking too long .. approximately 5.5 hours.
2. The chip utilization of just the memory is 47% of 1.8 million-gate equivalent chip.
The RAM is intended to have 8 synchronous write ports and 8 asynchronous read ports.
The code is shown here:
Any suggestion on how to reduce this high utilization to its normal range ? .. also reducing the synthesis time ..
Regards
I am trying to map my vhdl coded memory into Xilinx distributed RAM .. I'm using Xilinx Spartan-3A DSP chip (XC3SD1800A-4fg676) and Xilinx ISE 11.3.
I'm facing 2 problem:
1. Synthesis using XST is taking too long .. approximately 5.5 hours.
2. The chip utilization of just the memory is 47% of 1.8 million-gate equivalent chip.
The RAM is intended to have 8 synchronous write ports and 8 asynchronous read ports.
The code is shown here:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Entity Declaration --------------------------------------------------------
entity rregfile_dp is
port (
clk : in std_logic;
rst_n : in std_logic;
-- Write Port -------------------------------------
-- Port-0
wr_en0 : in std_logic; -- Write Enable
addrs0_wr : in unsigned (rg_addrs_width-1 downto 0); -- Write Addresses
data0_wr : in signed (rg_data_width-1 downto 0); -- Write Data
-- Port-1
wr_en1 : in std_logic; -- Write Enable
addrs1_wr : in unsigned (rg_addrs_width-1 downto 0); -- Write Addresses
data1_wr : in signed (rg_data_width-1 downto 0); -- Write Data
-- Port-2
wr_en2 : in std_logic; -- Write Enable
addrs2_wr : in unsigned (rg_addrs_width-1 downto 0); -- Write Addresses
data2_wr : in signed (rg_data_width-1 downto 0); -- Write Data
-- Port-3
wr_en3 : in std_logic; -- Write Enable
addrs3_wr : in unsigned (rg_addrs_width-1 downto 0); -- Write Addresses
data3_wr : in signed (rg_data_width-1 downto 0); -- Write Data
-- Port-4
wr_en4 : in std_logic; -- Write Enable
addrs4_wr : in unsigned (rg_addrs_width-1 downto 0); -- Write Addresses
data4_wr : in signed (rg_data_width-1 downto 0); -- Write Data
-- Port-5
wr_en5 : in std_logic; -- Write Enable
addrs5_wr : in unsigned (rg_addrs_width-1 downto 0); -- Write Addresses
data5_wr : in signed (rg_data_width-1 downto 0); -- Write Data
-- Port-6
wr_en6 : in std_logic; -- Write Enable
addrs6_wr : in unsigned (rg_addrs_width-1 downto 0); -- Write Addresses
data6_wr : in signed (rg_data_width-1 downto 0); -- Write Data
-- Port-7
wr_en7 : in std_logic; -- Write Enable
addrs7_wr : in unsigned (rg_addrs_width-1 downto 0); -- Write Addresses
data7_wr : in signed (rg_data_width-1 downto 0); -- Write Data
-- Read Ports --------------------------------------
-- Port-0
addrs0_rd : in unsigned (rg_addrs_width-1 downto 0); -- Read Address
data0_rd : out signed (rg_data_width-1 downto 0); -- Read Data
-- Port-1
addrs1_rd : in unsigned (rg_addrs_width-1 downto 0); -- Read Address
data1_rd : out signed (rg_data_width-1 downto 0); -- Read Data
-- Port-2
addrs2_rd : in unsigned (rg_addrs_width-1 downto 0); -- Read Address
data2_rd : out signed (rg_data_width-1 downto 0); -- Read Data
-- Port-3
addrs3_rd : in unsigned (rg_addrs_width-1 downto 0); -- Read Address
data3_rd : out signed (rg_data_width-1 downto 0); -- Read Data
-- Port-4
addrs4_rd : in unsigned (rg_addrs_width-1 downto 0); -- Read Address
data4_rd : out signed (rg_data_width-1 downto 0); -- Read Data
-- Port-5
addrs5_rd : in unsigned (rg_addrs_width-1 downto 0); -- Read Address
data5_rd : out signed (rg_data_width-1 downto 0); -- Read Data
-- Port-6
addrs6_rd : in unsigned (rg_addrs_width-1 downto 0); -- Read Address
data6_rd : out signed (rg_data_width-1 downto 0); -- Read Data
-- Port-7
addrs7_rd : in unsigned (rg_addrs_width-1 downto 0); -- Read Address
data7_rd : out signed (rg_data_width-1 downto 0)); -- Read Data
end entity rregfile_dp;
-- End of Entity Declaration -------------------------------------------------
-- Architecture Declaration --------------------------------------------------
architecture rtl of rregfile_dp is
type regfile_type is array (natural range <>) of signed (rg_data_width-1 downto 0);
signal raccum_reg : regfile_type (0 to (2**rg_addrs_width)-1);
begin -- architecture rtl
----------------------------------------------------------
-- Write Process
----------------------------------------------------------
proc_wraccum: process (clk, rst_n) is
begin -- process proc_wraccum
if rst_n = '0' then -- asynchronous reset (active low)
raccum_reg <= (others => (others =>'0'));
elsif clk'event and clk = '1' then -- rising clock edge
if wr_en0 = '1' then
raccum_reg(to_integer(addrs0_wr)) <= data0_wr;
end if;
if wr_en1 = '1' then
raccum_reg(to_integer(addrs1_wr)) <= data1_wr;
end if;
if wr_en2 = '1' then
raccum_reg(to_integer(addrs2_wr)) <= data2_wr;
end if;
if wr_en3 = '1' then
raccum_reg(to_integer(addrs3_wr)) <= data3_wr;
end if;
if wr_en4 = '1' then
raccum_reg(to_integer(addrs4_wr)) <= data4_wr;
end if;
if wr_en5 = '1' then
raccum_reg(to_integer(addrs5_wr)) <= data5_wr;
end if;
if wr_en6 = '1' then
raccum_reg(to_integer(addrs6_wr)) <= data6_wr;
end if;
if wr_en7 = '1' then
raccum_reg(to_integer(addrs7_wr)) <= data7_wr;
end if;
end if;
end process proc_wraccum;
----------------------------------------------------------
----------------------------------------------------------
-- Read Process
----------------------------------------------------------
data0_rd <= raccum_reg(to_integer(addrs0_rd));
data1_rd <= raccum_reg(to_integer(addrs1_rd));
data2_rd <= raccum_reg(to_integer(addrs2_rd));
data3_rd <= raccum_reg(to_integer(addrs3_rd));
data4_rd <= raccum_reg(to_integer(addrs4_rd));
data5_rd <= raccum_reg(to_integer(addrs5_rd));
data6_rd <= raccum_reg(to_integer(addrs6_rd));
data7_rd <= raccum_reg(to_integer(addrs7_rd));
----------------------------------------------------------
end architecture rtl;
-- End of Architecture Declaration -------------------------------------------Any suggestion on how to reduce this high utilization to its normal range ? .. also reducing the synthesis time ..
Regards
