Please, would like to have verilog wrapper example code

Hello,

I’m trying on using LatticeMico32 as a main CPU aiming to create a CPU that surround by my own peripheral IP module. The problem is when import custom IP module to a system, CPU platform builder (Lattice MSB) supports only Verilog and I know only VHDL. However the manual suggests that VHDL user can create Verilog wrapper to cover VHDL code before import to system. Can anyone please give me an example of Verilog wrapper code?
Ps. I know that there are VHDL to Verilog convertor but I would like to know how to wrap it.

Thank you very much in advance.

kurukuru said:

However the manual suggests that VHDL user can create Verilog wrapper to cover VHDL code before import to system. Can anyone please give me an example of Verilog wrapper code?

Click to expand...

Hi

both *.vhd and *.v files are in attachment.

Below code is Verilog wrapper to cover VHDL code of simple up counter
// VerilogWraper_upcounter_vhd.v
`timescale 1ns/100ps

module VerilogWraper_upcounter_vhd
(
input wire extClk,
input wire pbRstN, // active low reset input
input wire Enable,
output wire [07:00] Count
);

up_counter Instance_0
(
.cout ( Count ), // output [07:00]
.enable ( Enable ), // input
.clk ( extClk ), // input
.reset ( ~pbRstN ) // input active high reset
);

endmodule

Below code is up_counter.vhd. This code is taken form asic-world web site just to give you an example.

-------------------------------------------------------
-- Design Name : up_counter
-- File Name : up_counter.vhd
-- Function : Up counter
-- Coder : Deepak Kumar Tala (Verilog)
-- Translator : Alexander H Pham (VHDL)
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity up_counter is
port (
cout ut std_logic_vector (7 downto 0); -- Output of the counter
enable :in std_logic; -- Enable counting
clk :in std_logic; -- Input clock
reset :in std_logic -- Input reset
);
end entity;

architecture rtl of up_counter is
signal count :std_logic_vector (7 downto 0);
begin
process (clk, reset) begin
if (reset = '1') then
count <= (others=>'0');
elsif (rising_edge(clk)) then
if (enable = '1') then
count <= count + 1;
end if;
end if;
end process;
cout <= count;
end architecture;

HTH
--
Shitansh Vaghela

Hi,
Thank you very much Shitansh for your kindly reply. Would it bother if I ask more things? I would like to know where in Verilog code that I can place my to be wrapped VHDL code, before or after mapping Verilog pinout to VHDL pinout or wherever? And what if I have generic in my VHDL code?

Thank you very much.

kurukuru said:

I would like to know where in Verilog code that I can place my to be wrapped VHDL code, before or after mapping Verilog pinout to VHDL pinout or wherever?

Click to expand...

module test
(
// port list
);
/*
* Internal varilable decleration
*/
/*
* space for VHDL source instance
*
*/
endmodule

kurukuru said:

what if I have generic in my VHDL code?

Click to expand...

In VHDL generic is ued to give constraint to your design like maximum clock frequency or clock to output ...etc

while you are doing instance of VHDL code in verilog you need to write only port list. and generic parameter you have to pass through constaint file (*.sdc) during compilation and synthesis.

Let others correct me if l am wrong!!

HTH
--
Shitansh Vaghela

Thank you very much again for your kindly reply. I will try this as soon as I can.