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The Main Problem with latches is the STA/DFT incompatibility as "yeewang" said. Also glitches in the enable pin of the latches cause improper functionaing of the system. What RMM says is to avoid creating latches UNKNOWINGLY by defining a "else" condition for an if statement .. and default case for a CASE statement.
Latches on the other side takes less power,area compaerd to FFs
U cant do DFT/Scan in latches . also latches led to combinational feed back in your design , which also can led to unavoidable oscillations in circuit , causing your logic into TOSS.
if the design is not aware of the power, flip-flop is prefered. and almost all the latchs could be replaced by flip-flops without changing the function.
i think you can do it, but where you can use & where you cann't must be careful.
i don't use it, i'm afraid.
i have seen make 1 dff with 2 latch, but it's not asic.
latches are wondrous things, and are the solution to good designs, compact chips, and peace on earth. Three clear advantages of latches are:
1.Considerably smaller than D-type flip-flops
2.Provide anticipation of the data (for example, the decode of a latched address can begin before the latch is closed)
3.Lower power, compared with continuously clocked flip-flops.
If you do insist on a latch-based design, watch out for the following:
1.A glitch-free enable—remember that glitches on the enable can corrupt the latch’s data. If you are synthesizing the code to create the enable, consider seriously the direct instantiation of the gate that drives the enable to the latch. Don’t trust optimized equations!
2.Data input hold time—ensure that the data is held for long enough as you close the latch. If your latch enable is derived from a clock, the latch will lag the clock, requiring the latch’s D inputs to be held valid after the clock edge
Hello,
I have a critical path in my design. The combinatorial logic between two flipflops can not be reduced further to avoid setup violations. Any suggestions on this?
Hello,
I have a critical path in my design. The combinatorial logic between two flipflops can not be reduced further to avoid setup violations. Any suggestions on this?
You have few options here:
1. slow down the clock frequency
2. thighen your synthesis constrain to allow better optimization
3. use pipelining/ flattern in your design
4. change the design architecture/structure
On top of wufengbo's point's:
latch will relay the signal changes in its transparent phase. From the equation of P = C*V^2*f. It might burn more power (not necessary to be true)
You can use LSSD to make the scan possible for latch.
s0shinde: You are asking for a solution for the latch-base cycle stealing... pushing the cycle time across the latches' bounadries... please refer to your another post... I put some suggestions over there.
One of the main reasons that latches are not used in designs is due to combinational loop back which creates problems in simulation and results in synthesis and simulation mismatches. But if proper care is taken latches can be used.
The latch has the disadvantage of being "trnansparent" till the clock makes him latch the value of the input.
The FF samples the input on the risinf or falling edge of the clock.
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