Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Any fast method to checking floating node?

Status
Not open for further replies.
W

wccheng

Full Member level 5
Joined
May 16, 2004
Messages
287
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Activity points
2,710
Hi Folk,

Does C@dence provide any simulation method to check floating node of my circuit? Could you tell me how could I do it?

Thanks

wccheng
 

wccheng said:
Does C(at)dence provide any simulation method to check floating node of my circuit? Could you tell me how could I do it?
wccheng
Click to expand...
You don't need to simulate: It's already included in the schematic check, at least by default: You might check the setUp: In a schematic window - in the top menu - click Options -> Check... (or: Check -> Options... ), in the Schematic Check Options menu click Rules Setup ... , then in the Setup Schematic Rules Checks menu Logical options see that Floating Nets creates a warning or an error.
When you click Design -> Check and Save (X) , you should get appropriate warnings resp. errors for floating nets.
 

I am thanks for your reply. However, I have another question about floating problem. If I have a circuit because of architecture, it might create floating node in some status. How could I check it in a faster way? Because of large circuit design, I could not check all node one by one.

Thanks


erikl said:
wccheng said:
Does C(at)dence provide any simulation method to check floating node of my circuit? Could you tell me how could I do it?
wccheng
Click to expand...
You don't need to simulate: It's already included in the schematic check, at least by default: You might check the setUp: In a schematic window - in the top menu - click Options -> Check... (or: Check -> Options... ), in the Schematic Check Options menu click Rules Setup ... , then in the Setup Schematic Rules Checks menu Logical options see that Floating Nets creates a warning or an error.
When you click Design -> Check and Save (X) , you should get appropriate warnings resp. errors for floating nets.
Click to expand...
 

wccheng said:
If I have a circuit because of architecture, it might create floating node in some status. How could I check it in a faster way?
Click to expand...
By LVS .
 

LVS just could make sure the connection is same as schematic one. However, it could not solve the problem I mention before.

thanks

wccheng

erikl said:
wccheng said:
If I have a circuit because of architecture, it might create floating node in some status. How could I check it in a faster way?
Click to expand...
By LVS .
Click to expand...
 

wccheng said:
LVS just could make sure the connection is same as schematic one.
wccheng
Click to expand...
Right. If your schematic has no floating nodes and if your LVS matches, you may be sure that your layout doesn't have floating nodes, either. That is - among other items - the LVS is thought for.
 

Then, how could I fix this kind of hidden floating node problem?
 

wccheng said:
Then, how could I fix this kind of hidden floating node problem?
Click to expand...
So you got LVS errors and want to know how to fix them? There's no quick procedure for this AFAIK, unless you are experienced with handling the LVS error messages (no. of connections in schematic vs. no. of connections in layout). Otherwise standard methodology is partitioning: divide et impera!
 

Hi wccheng,

I think I more or less understand your floating nodes issue, but not completely.

Maybe if you illustrate your question with an example, we can better understand your problem.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top