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what is the best launguage for verification of the CPU?

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Dongbei

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what is the best launguage for verification of the CPU, vera, e, sugar, systemc??
 

i prefer systemverilog , e is also very good but specman is too expensive
 

It's not the language, it's the methodoloy. If you like a random sequence generator, specman is definitely the best choice. Wanna save money? Try www.testbuilder.net, CVE is great!
 

yes, it is the methodoloy. Could you give me a link about how to verify cpu design?
 

e,
and you must employ hardware accelerator to increase verification speed.
 

I got used to verilog a long time ago.
Now, I think vera and systemC is good for interfacing to synopsys' tools, and SystemVerilog and SystemC is more promising.
 

I prefer System Verilog for Assertions in CPU vealidation.
u can use System C thread programming also,
 

I don't agree with somebody who believe that the systemC or SystemVerilog is suitable to do verification. The biggest problem is about synthesis. You can use some high-level structures in these environment which are not synthesizable. I mean you, as a designer, have to write two codes 1) SystemVerilog compatible 2) synthesizable compatible. You may verify a CPU based on the SystemVerilog, but you have to change the design performed in the SystemVerilog to be synthesizable.
Hence, i recommend a methodology which is embedded in the design flow of a real design. If you use some specific verification tool like SpecmanElit of Verisity Co., you will write the code in VHDL/Verilog which will be your hardware. On the other hand, you write some properties or assertions to be checked in your hardware. You can expand the properties to cover some or all parts of a design.

Regards,
KH
 

Something should be special for verification of uP, since the soft part should be considered greately. There are some high level languages(like C based) suitable for this job, you can refer to those. You still need some soft simulator and emulators and so on. Normal testbench for asic is not enough, some tools will be helpful.
 

I also think systemC is promissing.
 

Vera is also good for verification ,for it's just like c,and easy to learn
 

Something should be special for verification of uP, since the soft part should be considered greately. There are some high level languages(like C based) suitable for this job, you can refer to those. You still need some soft simulator and emulators and so on. Normal testbench for asic is not enough, some tools will be helpful.
Click to expand...

What you said is another method to check a behavioral or algorithmic level verification. As i mentioned before, the biggest problem is synthesis. There is a large gap between abilities to synthesize a RT level design and a behavioral level design. If we can synthesize a C code to a hardware, so your method would be great. But this conversion has lots of problems.

Regards,
KH
 

yes, you are right. I think both are extremely important. what we do is careful simulate the behavioral level C codes and then translate them into RTL with predefined arch of circuit
 

i think systemC is the best
 

if you set up test bench, better use verilog, some task can use PLI.
But I think you are to write C model, so systemC or C all ok.
the simple the better.
 

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