rali
Newbie level 3
generic rom vhdl code
hi,
i want to implement a block rom with generic read width and read depth in vhdl.i'm using modelsim se.Can xilinx core gen block rom be used to have the generic read width and depth or should a vhdl code be written to infer block rom.The design is to be synthesized in xilnx virtex 2 fpga.
hi,
i want to implement a block rom with generic read width and read depth in vhdl.i'm using modelsim se.Can xilinx core gen block rom be used to have the generic read width and depth or should a vhdl code be written to infer block rom.The design is to be synthesized in xilnx virtex 2 fpga.