lt.data
Newbie level 4
fpga netlist
Hi, does anyone knows a way to produce a FPGA netlist in gate level?
Netlist with primitive gates like or, not, and... etc.
The xilinx netgen command produce the netlist with LUT, but i need the netlist in gate level.
I know that you can see in the ISE, through view Technology schematics when you double click on the LUT component, its gate level schematics,but can i do the same with netgen command?
does xilinx netlist format (XNF) or EDIF can do that?
thank a lot, lt.data.
Hi, does anyone knows a way to produce a FPGA netlist in gate level?
Netlist with primitive gates like or, not, and... etc.
The xilinx netgen command produce the netlist with LUT, but i need the netlist in gate level.
I know that you can see in the ISE, through view Technology schematics when you double click on the LUT component, its gate level schematics,but can i do the same with netgen command?
does xilinx netlist format (XNF) or EDIF can do that?
thank a lot, lt.data.
