LDO designs with or without external capacitor

ldo bypass cap

I am new to LDO designs, just did some reading up. Not clear about the practical choices of LDO with or without using external bypass capacitor.
A) Without external bypass capacitor, internal dominant pole
Pros: cost saving of the external bypass capacitor
Cons: 1) Need internal compensation; could use DFC (Damping Factor Control) to widen the frequency response, use dynamic bias current and/or pole-zero tracking of pass transistor output current to optimize the frequency response and stability.
2) What if the user adds in additional capacitor trying to improve noise/ripple ?
Or user may not knowing do that because the chip Vdd supply connecting to the LDO output may have Vdd-Gnd big internal on-chip bypass capacitor.

B) With external bypass capacitor
With external bypass capacitor using capacitor ESR as zero, this still becomes the earlier case A, and have the same cons without the pros.
I am more thinking of the case of external bypass capacitor as dominant pole.
Pros: 1) As long as sufficient capacitor is used, it is stable. User add additional capacitor improves noise/ripple and does not cause stability problem, though may slow down transient response.
2) Dynamic bias current and/or pole-zero tracking can still be used to optimize the frequency response.
Cons: cost of the external bypass capacitor

What is the practical good choice of designing LDO with or without external capacitor ?
My application for these LDOs are for highly integrated PMIC targeting for cellphones.
Welcome any insightful or practical comments. Thank you very much.

dynamic zero ldo

I am new to this LDO area, and was trying to get some practical insights into deciding which is the better way of having the dominant pole at the LDO output or dominant pole generated internally. The application is for cellphone PMIC (Power Management IC) where there are 14 to 18 integrated LDO on the PMIC chip.
I was very surprised that there are no comments nor feedback on this very key design choice. I am 100% sure that the members in this profession have ran into and thought hard about this same issue.
Aside from not willing to disclose trade secrects and professional advantages, it would be very enlightening to know where and why the dominant pole of LDO is, especially if it is for cellphone applications.
Hope I did not offend anyone, and thanks in advance for any feedback.

cons and pros of capacitor

I am not deply experienced in LDO design, however, as far as I remember is the dominant pole created by the internal error amplifier (normally an opamp).
And, because of loop stability with a feedback factor which is larger than 1 (transistor gain) a load cap with an appropriate ESR is used. Thereby, the loop gain is decreased and goes trough the 0-dB-line with a slope of app. -20 dB/dec.

ldo dynamic load response

The dominant pole in the LDO without compensantion is the output pole of the error amplifier. The frequency response may be sufficient for your application without any compensation if the load charge won't be below a specific value (ie below 50-100 uA). If this is the case you may not need to worry with the capacitors, you will have a fast and stable LDO. If your charge falls below this values (or other calculated by you) you will need to compensate your regulator. there are several means to do that, active capacitor compensation, current controlled frequency response or typical output capacitor compensation. Considering your application is a highly integrated PMIC you will always love to have less area, thus you dont want any off-chip passive stuff.