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input and output declaraion as integer in verilog

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Mkanimozhi

Mkanimozhi

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verilog input output

Hi,
In verilog shall we declare input and outputs as integer ,if we do na,how to declare,reply me any one.


kanimozhi.m
 

verilog integer

Inputs and outputs of modules are wires or registers. Not integers.

Tasks can have integer inputs, but are not synthesizeable.



r.b.
 

verilog input integer

hi,

as per my knowledge integers are synthesizable and will inferr 32bit register.
Pls check and update..

Keshav
 

integer verilog

As I understand it, integers are synthesizeable but cannot be used to define the inputs and outputs of modules. Only wire, reg and inout, or "logic" in the case of System Verilog, can be used for the port definitions.

I just tried defining a port as an integer and it did not work for Synplify Pro.

However, if it works for you, I'd be interested to know what synthesis tool you are using.

r.b.
 

output register verilog

Try using

input [31:0] signal_name;
output integer signal_name1;
 

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