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Maximize the beta of bipolar transistor in CMOS technology

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neoflash

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β of the planar bipolar transistors is a big headache of the modern CMOS technology.

Accoring to the principle theory, β is a function of base area width. Is there any paper/book report any tricks for maximizing the β with layout optimization?
 

In std. CMOS technologies you just have vertical pnp transistors available, and the base width is the difference between n-well depth and S/D p+ implant junction depth, i.e. only process dependent, not manipulable by design.

Dedicated analog CMOS technologies also allow for lateral BJTs, but here the base width is limited by design rules, enabling higher, but still limited beta.

To do even better, you'd need your own CMOS tech., or at least the permission to intelligently circumvent the design rules ;-)
 

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