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a problem about pipelined ADC

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zouwanghui

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I have read this from some material:
without trimming or calibration, the resolution of pipelined ADCs is limited to 10bit. the main reason is mismatching.

what I want to know is how to make this conclusion with derivation?
does any materials about this on web?

thanks
 

There are plenty of papers dicussing the non-idealities of pipelined ADC. One of the major limitation for untrimed 10-bit accuracy originates from the capacitor mismatch at the MDAC stage.

Willy
 

There are many problem with induce error in the ADC , but the Key factor is MDAC . Capacitor mismatch ,, It's mean gain mismatching , other like
layout mismatching will increase even harmonic ...
So that if you want to well 10bit ADC , I think the capacitor value selcet is very important .

Ps , you can see the foundry's capacitor matching report
 

The main problem is from MDAC. You can refer to this book: CMOS Data Converters for Communicaiton.
 

Hi
The capacitor mismatch is one of the non-idealities also the open loop gain of the MDAC affects the resolution too.

zouwanghui said:
I have read this from some material:
without trimming or calibration, the resolution of pipelined ADCs is limited to 10bit. the main reason is mismatching.

what I want to know is how to make this conclusion with derivation?
does any materials about this on web?

thanks
Click to expand...
 

I think you want to do triming . I think you must add
the cap value , In my experiment , we do 100MHz.10bit/ADC , the first MDAC , I will use 1pf ~
1.2pf . Becasue it will get well matching ..

and you can do the post-sim , and check the parasitic cap with Cs/Cf , this is key factor in the first
stage and second stage .
 

The errors in ADC could be due to offset of the op-amp,cap mismatch ,comparator offset .The killer would be cap mismatch in MADC .

consider one capacitor mismatch at a time .Let's say Cs=C+/- delta and calculate residue with new cap .The residue show that Closed loop gain varies with cap mismatch .

This has be trimmed using Analog/Digital calibration techniques for first 3 or 4 stages .

Can any one highlight on Digital calibration techniques ? .
 

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