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  1. #1
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    verilog image processing

    Hi
    I want to implement an image processing algo using verilog... I have a design module that calculates histogram of image and gives 2 output 'nout' and 'x'. nout is no.of pixels in a bin while x is centre of bin. i have 10 elements of nout and x each for 10 bins each nout of 12 bits and x of 8 bits. i declared it in verilog as:

    module myimhist(nout,x,y,nbin);

    parameter length_nout=12; //length of nout
    parameter length_xxy=8; //length of x
    parameter length_nbin=4; //length of nbin
    parameter depth=10;

    output [length_nout-1:0] nout[0:depth-1]; //output
    output [length_xxy-1:0] x[0:depth-1]; //output

    but it gives syntax error when simulated in modelsim for the 2 outputs..... can anybody help me out that how to out these two registered outputs???
    Plz reply as soon as possible.

    •   Alt19th September 2008, 07:03

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  2. #2
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    image processing using verilog programming

    I am not sure, but it might be that you may not have multidimensional arrays as ports.
    Kr,
    Avi



    •   Alt19th September 2008, 10:20

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  3. #3
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    image processing verilog

    Hi,
    The verilog doesn't support multi dimensional port declaration. I think this feature is available in System verilog.

    Try to change the output port declaration and check.



    •   Alt25th September 2008, 16:35

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  4. #4
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    image processing algorithm

    hey,can any one please help me how to convert multidimensional array into one dimensional array....
    i'm new in FPGA and using system generator in matlab..
    i want to get camera data into a FPGA...
    since its RGB it has dimensions of [mxnx3]
    but the GATE IN block allows only one dimension
    so can u plz help me to solve the problem



  5. #5
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    Re: image processing algorithm

    Quote Originally Posted by bsmaldeniya View Post
    hey,can any one please help me how to convert multidimensional array into one dimensional array....
    i'm new in FPGA and using system generator in matlab..
    i want to get camera data into a FPGA...
    since its RGB it has dimensions of [mxnx3]
    but the GATE IN block allows only one dimension
    so can u plz help me to solve the problem
    I am having the same problem. Have you solved yours?



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