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high resolution (15 bit) delta sigma ADC simulation problem

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jowong1

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cadence sigma delta reltol

I am designing a rather high resolution (>15bit) delta sigma ADC. I have a design that's working in MATLAB and I am trying to build the same thing in cadence using Verilog A modeling. Every component I have now is ideal and in verilog A code, so that means no transistors, no resistors and no capacitors. I am using the function laplace_nd to model my loop filter, however, the SNRs I am getting is off from what I got in MATLAB and the max stable input amp is off as well. I have tried the following

1. Tighten reltol and abstol
2. reduce the max time step to 1ps, running under moderate (this is giving me convergence issue)

But they are not solving my problems. Does anyone have any idea on what else I can try?

Thanks
 

delta sigma adc simulation tool

How do you get the SNR from your simulation result?
 

how to obtain high resolution in delta sigma adc

I take the PSD and then integrate...I did that in both matlab and cadence

Thanks
 

Re: high resolution (15 bit) delta sigma ADC simulation prob

it is continuous-time sigma-delta modulator you have modelled? what about psd you have got? what difference compared to that from cadence? try errpreset=convative as well.
 

Re: high resolution (15 bit) delta sigma ADC simulation prob

The difference in SNR actually depends on the order of my DSADC. For 3rd order, the difference is about 5dB (I suspect if I get more data points, I can have the 2 match). But for 5th order, the difference is much more (>10dB) , and the max stable input amp in Matlab is 0.8V while in Cadence is like 0.4V. I have tried setting to conservative, but it's still the same thing for the 5th order. If i further tighten the max step size, then I will have convergence issue.

Thanks and appreciate any ideas

and yes, it's a continuous time
 

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