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how to generate timing for SC circuit?

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leohart

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how to generate timing for SC circuit in case having only a clk input for that

do you guys use digital STC lib to synthesize the logic?
 

you can find answer in almost every textbook. normally you need to generate nonoverlapping logic first, by delaying the original clock and then pass it through NAND gate with the original signal. or more complicated one.

then you may estimate the load of control logic, and scale the output buffer.
 

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    leohart

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hi, nus_lin can you elaborate more?
how to delay the original clock?and why through nand gate?

I've read razavi,gray,etc. but they havent mentioned this techniques for timing generation...would you give me a reference book list? THX
 

CLK and CLKB to drive a RS trgger, then the RS trigger will give an overlap clock. Inverse the overlap clock you can get non-overlap. You can add buffers in RS trigger's loop to control the non-overlap time.
 

design a counter,
connect its output to the decoder input
now you can get different timming
 

here is an example of a simple non-overlapping clock generator. CK is the input clock, CKA and CKB are the two non-overlapping outputs.

Added after 1 minutes:

here is an example of a simple non-overlapping clock generator. CK is the input clock, CKA and CKB are the two non-overlapping outputs.

56_1218228584.jpg
 

JoannesPaulus said:
here is an example of a simple non-overlapping clock generator. CK is the input clock, CKA and CKB are the two non-overlapping outputs.

Added after 1 minutes:

here is an example of a simple non-overlapping clock generator. CK is the input clock, CKA and CKB are the two non-overlapping outputs.

56_1218228584.jpg
Click to expand...

???Seems this circuit can only generate some pulse. The RS trigger is a NAND loop, but not an AND loop.
 

hi guys, you are all talking about generation of simple two phase nonoverlaped clk, do most of the SC ckts only require such simple timing?

What I meant for timing generation is like in this timing diagram
 

I think for most application SC circuits use these simple 2 phase ck gen is ok. What's your application???

I've just finished one clock circuit to generate 4 phase non-overlap for SC. However I have no good idea too and just use 2X clock rate and tranditional 2 non-overlap phase clock generator to fulfill the job.
 

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    leohart

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this is a timing diagram for cmos image sensor column readout, it uses a simple sc circuits too(although there is no opamp in it)

can you post a timing diagram for the 4 non overlapped clock？
 

leohart said:
this is a timing diagram for cmos image sensor column readout, it uses a simple sc circuits too(although there is no opamp in it)

can you post a timing diagram for the 4 non overlapped clock？
Click to expand...
Sorry, I don't know how to post a picture.
To be simplified. It have a 2X clock rate input, so when you followed it with a tranditional 2 non-overlap phase generator, it will output non-overlap clock pulse width is the <1/4 of 1X clock cycle. Then, use 1X clock (just halfed the input frequency) as an enable signal to switch between PH1/2 and PH3/4.
 

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    leohart

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you can generate almost any clocking scheme once you understand the basic principle of the schematic I gave you!
 

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    leohart

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JoannesPaulus said:
you can generate almost any clocking scheme once you understand the basic principle of the schematic I gave you!
Click to expand...

can it generate the timing I've posted?
 

The schematic which JoannesPaulus post is wrong,

Added after 5 minutes:

Even numbers of NOT gate follow the NAND,not odd number,AND LOOP doesn't work.

Added after 2 minutes:

To ricklin:

what's your reference for 4 phase nonoverlapping clock design?
 

kennyg said:
To ricklin:

what's your reference for 4 phase nonoverlapping clock design?
Click to expand...

Do you mean reference paper or data? This is only a temporary solution which comes from the conventional 2-phase clock gen and requires 2X clock on system level. So no reference for such type and may have certain risk ( the 4 phase need to be aligned with the 1X clock).
 

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