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VHDL question (process implementation as FSM)

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TekUT

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Dear all,
I'm learning VHDL, after some simple example I'm going to closely look at the implementation of this one shot delay generator, here the code:

Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- entity definition

entity pulse_5clk is
	port(
		clk, reset: in std_logic;
		go, stop: in std_logic;
		pulse: out std_logic
	);
end pulse_5clk;

-- architecture definition

architecture fsmd_arch of pulse_5clk is
	constant P_WIDTH: natural := 5;
	type fsmd_state_type is (idle, delay);
	signal state_reg, state_next: fsmd_state_type;
	signal c_reg, c_next: unsigned(3 downto 0);
begin
	-- state and data registers
	process(clk, reset)
	begin
		if (reset = '1') then
			state_reg <= idle;
			c_reg <= (others => '0');
		elsif (clk'event and clk='1') then
			state_reg <= state_next;
			c_reg <= c_next;
		end if;
	end process;
	-- next state logic & data path functional units/routing
	process(state_reg,go,stop,c_reg)
	begin
		pulse <= '0';
		c_next <= c_reg;
		case state_reg is
			when idle =>
				if go='1' then
					state_next <= delay;
				else
					state_next <= idle;
				end if;
				c_next <= (others => '0');
			when delay =>
				if stop='1' then
					state_next <= idle;
				else
					if (c_reg = P_WIDTH - 1) then
						state_next <= idle;
					else
						state_next <= delay;
						c_next <= c_reg + 1;
					end if;
				end if;
				pulse <= '1';
		end case;
	end process;
end fsmd_arch;

all is working right but I've a question, into the second process definition (the state logic & data path) I can see this statement:

Code:
pulse <= '0';

then, the output signal should be set to 0 but into the simulation this never occour and the behaviour of the output signal look right then the ouput signal goes to 0 only after the counter has elapsed.

Here in attachement the simlated waveform.

Someone can gimme some explanation about this type of behaviour (why the statement pulse <= '0' don't force to 0 immediatly the output signal when the execution of the last process take to run?).

Thanks in advance
Powermos
 

Dear all,
I've taken a new reading of process notes and I've see that into the process all the signal assignement are updated at the end of the process then bcz I've another assignement statement as pulse <= '1'; this win on the first one and the signal state was set to 1 and not to 0. I think to have understand the point, someone can confirm that I'm right?

Thanks in advance
Powermos
 

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