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Some DC questions about libraries and clock

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fan1200

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I am new in DC and have some questions.Plz help me.
I want to change verilog HDL to the netlist,then change the netlist to layout.
Now I use design vision to change verilog HDL to the netlist.
Here is the first question.When I DC the circuit ,there is an Error:Could not read the following target libraries:your library.db
Can I get the library from the foundry or synopsys？
The second question:
I design a counter which has 2 clocks of the same frequency but with a phase difference.When I DC it ,the clock_ and reset_ are floating(They don’t connect to any other net ).Is there something wrong with the verilog HDL　which I wrote?


Thank YOU so much.
 

Some DC quesitions

You need to set the link library and target library path. Use the following commands in the dc_shell:

dc_shell> set link_library_path $SYNOPSYS/libraries/syn/lsi_10k.db

dc_shell> set target_library_path $SYNOPSYS/libraries/syn/lsi_10k.db

These are standard libraries that come with DC.. You can add these commands to your .setup file also to avoid typing every time..

Added after 2 minutes:

Can you elaborate your second question a bit more with screenshots and your RTL..
 

Re: Some DC quesitions

To asicganesh

Thank you for your answer.
so you mean there is nothing about process when I change verilog HDL to the netlist.

the secound question

I add a file
 

Some DC quesitions

fan1200 I didn't get you.. I think you got confused.. There is ofcourse standard flow/process to generate netlist..

Generally target_library should point to the library provided by your silicon vendor.. Couple of libraries from LSI, TSMC come embedded with DC which can be found in the path.. During mapping DC will Choose functionally-correct gates from this library and Calculate the timing of the circuit using vendor-supplied timing data for these gates

On the other hand link library is used to resolve sub-design references.. hope now it clears your doubt.

So if you have a vendor specific library.. you should set these env variables to point them

Added after 15 minutes:

Can I have a look at the RTL also..
 

Re: Some DC quesitions

module counter(out,out_,ck,ck_,res,res_);

input ck,ck_,res,res_;
output [7:0] out;
output [7:0] out_;


wire ck;
wire ck_;
wire res;
wire res_;
wire [7:0] out_;
reg [7:0] out;


assign ck_=~ck;
assign out_=~out;
assign res_=~res;


always @(posedge ck ) begin
if(res==1'b1&res_==0)
out <= 8'h0;
else
out <=out+8'h1;
end


endmodule
 

Some DC quesitions

Try removing ck_ and res_ as input ports..

hope that will solve the case..
 

Re: Some DC quesitions

How to remove ck_ as a input port?
I have remove res_ as a input port.
module counter(out,out_,ck,ck_,res,res_);

input ck,ck_,res,res_;
output [7:0] out;
output [7:0] out_;
wire ck;
wire ck_;
wire res;
wire res_;
wire [7:0] out_;
reg [7:0] out;

always @(posedge ck ) begin
if(res==1'b1&res_==0)
out <= 8'h0;
else
out <=out+8'h1;
end

assign out_=~out;

endmodule

but how to write differential signal as input port?

I try to write it as always @(posedge ck and negedge ) begin
but it is error.
can anyone help me?
 

Some DC quesitions

fan1200 u generate phase shifted clk and reset internally..

u dont need it as input right.. change ur code like this..
---------------
module counter(out,out_,ck,res);

input ck,res;
output [7:0] out;
output [7:0] out_;
-------------
 

Re: Some DC quesitions

TO asicganesh

I design a system which has to use differential signal .So before the counter there is something whose output signals are differential signals as input signal in the counter.
 

Some DC quesitions

fan1200

ok then dont drive these input pins(ck_ and res_) in your RTL...

Let me know if u still face the same problem after synthesis..

module counter(out,out_,ck,ck_,res,res_);

input ck,ck_,res,res_;

output [7:0] out;
output [7:0] out_;

wire ck;
wire ck_;
wire res;
wire res_;
reg [7:0] out_;
reg [7:0] out;

always @ (posedge ck) begin
if (res==1'b1&res_==0)
out <= 8'h0;
else
out <=out+8'h1;
end

assign out_=~out;

endmodule
 

Re: Some DC quesitions

the result of DC is upload.
so the port of ck_ does not connet to anything.

what shall I do?
 

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