echo47
Advanced Member level 6
The attributes in the following Verilog snippet cause fatal syntax errors in ModelSim 5.8. Is this my fault, or a ModelSim bug? Xilinx XST accepts it. If I rewrite it to eliminate the 'generate' loop, ModelSim accepts the attributes, and correctly ignores them. (The attributes are for Xilinx ISE.)
input [7:0] inp, inn;
wire [7:0] tmp;
output [7:0] outp, outn;
genvar n;
generate
for (n=0; n<8; n=n+1) begin : bufs
(* IOSTANDARD="LVDS_25" *) IBUFDS ibuf (.I(inp[n]), .IB(inn[n]), .O(tmp[n]));
(* IOSTANDARD="LVDS_25" *) OBUFDS obuf (.I(tmp[n]), .O(outp[n]), .OB(outn[n]));
end
endgenerate
input [7:0] inp, inn;
wire [7:0] tmp;
output [7:0] outp, outn;
genvar n;
generate
for (n=0; n<8; n=n+1) begin : bufs
(* IOSTANDARD="LVDS_25" *) IBUFDS ibuf (.I(inp[n]), .IB(inn[n]), .O(tmp[n]));
(* IOSTANDARD="LVDS_25" *) OBUFDS obuf (.I(tmp[n]), .O(outp[n]), .OB(outn[n]));
end
endgenerate