govandi999
Newbie level 4
vhdl code for crc
We have to design a module which is a simple CRC-5 check sum circuit that will implement the polynomial (1 + x2 + x5). This polynomial is used for error correction in USB. The block diagram is as follows:
We have to design a circuit that takes the 32 bit input and after 32 cycles produces the 5 bit CRC. The operation of the circuit is explained below
1) Start ← 1
2) The Din is used to calculate the CRC for the next 32 clk cycles. At each cycle
Dout <= Din
3) The CRC is output during the next 5 cycles.
At each clock cycle the CRC is calculated as follows
NewCRC(0) := DIN xor OLDCRC(4);
NewCRC(1) := OLDCRC(0);
NewCRC(2) := DIN xor OLDCRC(1) xor OLDCRC(4);
NewCRC(3) := OLDCRC(2);
NewCRC(4) := OLDCRC(3);
We have to write a VHDL code for the CRC generator.
I have written the following code but there is some problem, can you please correct it.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CRC5 is
port ( START : in std_logic;
CLK : in std_logic;
DIN : in std_logic;
DOUT : out std_logic
);
end CRC5;
architecture BEH of CRC5 is
signal temp : std_logic;
SIGNAL NewCRC : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL OLDCRC : STD_LOGIC_VECTOR(4 DOWNTO 0);
begin
PROCESS (CLK)
VARIABLE COUNT : INTEGER := 0;
begin
IF (CLK'EVENT AND CLK ='1') THEN
IF (START ='1') THEN
temp <= Din;
Dout <= temp;
COUNT := COUNT +1;
IF (COUNT = 32) THEN
NewCRC(0) <= temp xor OLDCRC(4);
NewCRC(1) <= OLDCRC(0);
NewCRC(2) <= temp xor OLDCRC(1) xor OLDCRC(4);
NewCRC(3) <= OLDCRC(2);
NewCRC(4) <= OLDCRC(3);
end if;
end if;
end if;
end process;
DOUT <= NewCRC(0);
DOUT <= NewCRC(1);
DOUT <= NewCRC(2);
DOUT <= NewCRC(3);
DOUT <= NewCRC(4);
end BEH;
We have to design a module which is a simple CRC-5 check sum circuit that will implement the polynomial (1 + x2 + x5). This polynomial is used for error correction in USB. The block diagram is as follows:
We have to design a circuit that takes the 32 bit input and after 32 cycles produces the 5 bit CRC. The operation of the circuit is explained below
1) Start ← 1
2) The Din is used to calculate the CRC for the next 32 clk cycles. At each cycle
Dout <= Din
3) The CRC is output during the next 5 cycles.
At each clock cycle the CRC is calculated as follows
NewCRC(0) := DIN xor OLDCRC(4);
NewCRC(1) := OLDCRC(0);
NewCRC(2) := DIN xor OLDCRC(1) xor OLDCRC(4);
NewCRC(3) := OLDCRC(2);
NewCRC(4) := OLDCRC(3);
We have to write a VHDL code for the CRC generator.
I have written the following code but there is some problem, can you please correct it.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CRC5 is
port ( START : in std_logic;
CLK : in std_logic;
DIN : in std_logic;
DOUT : out std_logic
);
end CRC5;
architecture BEH of CRC5 is
signal temp : std_logic;
SIGNAL NewCRC : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL OLDCRC : STD_LOGIC_VECTOR(4 DOWNTO 0);
begin
PROCESS (CLK)
VARIABLE COUNT : INTEGER := 0;
begin
IF (CLK'EVENT AND CLK ='1') THEN
IF (START ='1') THEN
temp <= Din;
Dout <= temp;
COUNT := COUNT +1;
IF (COUNT = 32) THEN
NewCRC(0) <= temp xor OLDCRC(4);
NewCRC(1) <= OLDCRC(0);
NewCRC(2) <= temp xor OLDCRC(1) xor OLDCRC(4);
NewCRC(3) <= OLDCRC(2);
NewCRC(4) <= OLDCRC(3);
end if;
end if;
end if;
end process;
DOUT <= NewCRC(0);
DOUT <= NewCRC(1);
DOUT <= NewCRC(2);
DOUT <= NewCRC(3);
DOUT <= NewCRC(4);
end BEH;