adamba
Newbie level 1
virtex-ii pro ddr 512 mb
My question: How can I write to DDR SDRAM from a custom IP core on the PLB Bus in a Virtex II Pro FPGA?
Background:
I am developing a custom IP core for a Virtex II Pro based system (the Xilinx XUP board). This core captures video data using the Digilent VDEC1 board at a pixel rate of 13 MHz. I would like to write several video frames to memory and process them in the Power PC processor.
Right now my core captures video and attempts to send it to the PPC using the PLB FIFO IPIF. However, there are several problems with this approach. It turns out that reading this data from the FIFO in software is extremely slow, so the FIFO fills up before I can read all of the pixels out of it (resulting in lost pixels and unusable frames). Also, there is only enough memory in the FIFO to store about one image frame (360x240 resolution), so it could not serve as a multi-frame buffer (and I need about 8 frames to do my processing)
Therefore, I would like to write the image data directly to DDR SDRAM from my custom IP core. I have 512 MB installed on the board, and I'm able to access it in C using the plb_ddr core. However, I am not sure how I can get my custom core to write to the DDR using the PLB bus.
If anyone could point me in the right direction, I would really appreciate it. I know that I will need to make my custom core a "Master" on the PLB bus and possibly use DMA, but I can't find a good example on how to read/write to memory.
Thanks.
My question: How can I write to DDR SDRAM from a custom IP core on the PLB Bus in a Virtex II Pro FPGA?
Background:
I am developing a custom IP core for a Virtex II Pro based system (the Xilinx XUP board). This core captures video data using the Digilent VDEC1 board at a pixel rate of 13 MHz. I would like to write several video frames to memory and process them in the Power PC processor.
Right now my core captures video and attempts to send it to the PPC using the PLB FIFO IPIF. However, there are several problems with this approach. It turns out that reading this data from the FIFO in software is extremely slow, so the FIFO fills up before I can read all of the pixels out of it (resulting in lost pixels and unusable frames). Also, there is only enough memory in the FIFO to store about one image frame (360x240 resolution), so it could not serve as a multi-frame buffer (and I need about 8 frames to do my processing)
Therefore, I would like to write the image data directly to DDR SDRAM from my custom IP core. I have 512 MB installed on the board, and I'm able to access it in C using the plb_ddr core. However, I am not sure how I can get my custom core to write to the DDR using the PLB bus.
If anyone could point me in the right direction, I would really appreciate it. I know that I will need to make my custom core a "Master" on the PLB bus and possibly use DMA, but I can't find a good example on how to read/write to memory.
Thanks.
