Tips for noise isolation and guard ring strategies

Ok I've read through lots of posts regarding noise isolation and guard ring strategies and I like to add some import points:

Without doubt the one thing that layout people get wrong is guard rings. Very wrong in fact. Let's look at some examples:

1. What potential do I tie the inside of my guard ring to? i.e. the ptap connection

- Local ground?

I've seen this done lots and lots of times. But what are you actually doing
when you do this?
So you've went through all the trouble of creating guard rings and now you've
just shorted them out by coupling all the noise in main p-substrate to you're
(supposedly) quiet substrate.

You absolutely NEVER tie inside the guard ring to outside the guard ring.

Therefore there must be a different tap for the 'quite' p-subs. e.g. VSUB.
So a good strategy is to have VSUB(quite) and VSS(noisy) star-connected
back to a pad. Better still if you can have two package pins and two bond
pads!

2. Another important question is what potential do I tie the NWELL quard ring to?

- VDD?

Again I've seen this done lots of times. If you tie the nwell guard ring to vdd,
i.e. the same vdd that all the active (noisy) devices share, then you've just
coupled all that noise INTO your (supposedly) quite substrate. So the
very thing you were trying to negate you have in fact made worse.

Again you need a quite potential for the nwells.

So to summarize a good strategy for guard rings:

A separate (quite) potential for the substrate inside the guard ring and a separate
(quite) potential for the nwell itself.

Hope this helps,

- Aio -

Re: Noise Isolation

Yah, Aio told very good point. Recently in some of our projects we are also following.

But I can say it's not only the prblem with Layout engineer. I am not only saying this as a layout engineer.

whenever we need to follow this convention in the flow itself. It's should be pointed in circuit also. Any way one person is not going to make the total chip. For each and every IP they have to includ these quite substrate pins and they have to connect them in Chip level.

Re: Noise Isolation

I completely agree Varma. The strategy HAS to be put into place at the very beginning, i.e. extra pins for the quite potentials etc..

The point is though that it is easy to change the noise strategy later on though if it's needed ( as some designers will argue the body effect that can be created if the mos bulk and source connection is separated), but it's extremely difficult to include these separate pins later on in the design/layout of the chip.

..btw for all you designers out there - Is it absolutely possible to have a separate bulk and source connection and have practically no body effect ...

Re: Noise Isolation

So we can say like, If we have some 4 power supplies like AVDD33, AVDD25, AVDD18 and VDD. We should have the same number of Substrate Powers also, right ?

But my question is, how much is it difficult to get each and every power line of the substrate to the pad ?

And also how we can decide the width of the these substrate powers, Do we need to maintain as same as the original powers ? if so is it possible ?

Bcoz sometimes, for original power lines only we may strugle to findout space and maintian the current ratings.

Re: Noise Isolation

Number of substrate powers:

We only really need one quite substrate power IF and ONLY if we as layout engineers have ensured that we have done a good job in ensuring that the signal is quite all the way back to the pad.
The problem arises though that you may have done an excellent job in your block but then in another block someone else has done a poor job and then at the toplevel these quiet powers are joined up and star-connected back. All the noise in the poor block is coupled into the good block.
A good strategy therefore maybe to have separate VSUB connections for the toplevel blocks and all these are then star-connected back individually to the pad.

Width of VSUB:

It's important to realize that what you're really trying to do is to create a (very) low impedance path off chip. Therefore low resistance is important. Reducing L is important and reducing W will also lower resistance but this will also increase parasitic capacitance. I'd always discuss the width of VSUB with the designer first.

Added after 1 minutes:

Edit to above comment - I meant increasing W and not decreasing it!

Re: Noise Isolation

yah that is correct, but what i mean to ask you is.

For suppose I am doing one PLL. In that I have 4 different power supplies.
AVDD33, AVDD25, AVDD18, DVDD. In this case I can't really use the one substrate connection to all the internal blocks right?

If I do like that, Definetly circuit engineer will cry.
He says my circuit woudn't work. Bcoz you are giving source diffrent and bulk different supplies. Yah it's correct only. Bcoz all the power supplies are not with same voltage levels. From my understanding we should have same number of Substrate power supplies too. Then only we can maintain the same supply to source and bulk. Is this correct or no ?

And coming to width, what ever you said is correct.
But my question is we should have some percentage of width from the original right.
I mean if designer says, I don't mind with the width of the bulk power. I only see for the source power, something like that.

What we can do ? By our knoloedge how we can put. How we can trade off that one.

Re: Noise Isolation

adrianos said:

You absolutely NEVER tie inside the guard ring to outside the guard ring.

...

So to summarize a good strategy for guard rings:

A separate (quite) potential for the substrate inside the guard ring and a separate
(quite) potential for the nwell itself.

Click to expand...

I don't see any reason to use a separate pin for guard rings and substrates for analogue circuits. Do you have any data to show that the substrate surrounding analogue circuits can couple significant noise to guard rings if both are tied to the same pin?

I would never share digital and analogue power supplies, but I share analogue supplies all the time.

Re: Noise Isolation

roadbuster:

From above posts you may already got why we need to seperate powersupply.
As per your statement, If we run seperate power supply for gurardrings only....there is no use. Becoz by using guardrings we are not going to inject more noise into power.

But you have to connect your substrate connections as well to the Bulk power supply. Then you are going to reduce the substrate noise into the power.

One more thing is, If you are talking about Digital and Analog.

In Digital, The power suppliy noise is very less than the substrate noise. Bcoz in that every tratsistor (i.e Almost) switching ones only. And all nets also switching ones only.
that to with high speed. All your noise because of the total circuitury, will give effect on substrate. So there is no big issue in Digital regarding this noise isolation.

Coming to Analog, Situation is diffrent. All your noise will be power supply only. It will automatically comes from out side world and pad. Guess it helps. Correct me if I am wrong. Thank You.

Re: Noise Isolation

if I do like that, Definetly circuit engineer will cry.Very Happy
He says my circuit woudn't work. Bcoz you are giving source diffrent and bulk different supplies.

Click to expand...

The reason that some designers don't like separate bulk and source potentials is that is creates a body effect which can cause variations in the Vt. The body effect is created because you now have created a cap between the source and bulk.

REM: cap = two plates at different potentials separated by an insulating layer.

If fact though we can make this cap very small by reducing the resistance of the source connection (which we should do anyways).

For suppose I am doing one PLL. In that I have 4 different power supplies.
AVDD33, AVDD25, AVDD18, DVDD. In this case I can't really use the one substrate connection to all the internal blocks right?

Click to expand...

In this example there are 4 substrate connections used but don't forget it really is just on substrate at the end of the day! (unless you're using deep-nwell)

Re: Noise Isolation

Ptap should be connect to GND, but Nwell can also connect to GND.
But I think Nwell connect VDD is better.

Re: Noise Isolation

:?:

Could you anybody recommend me software tools (preferably from Cadence) to be used for substrate noise analysis. Are there any tutorials on them?

Thanks.