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How to decrease the delay time of this high speed comparator

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gaom9

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Hi,
How to decrease the delay time of this high speed comparator, please?
In my design, the delay time from input to output is 11ns when the load is 5pf and overdrive voltage is 10mv, I want to decrease it below 10ns.
In my design, the delay time from input to latch output is 5.8ns, how to decrease it, and the delay time from latch output to output is nearly 5ns.
In my design, the gain of preamp is 2, the current of latch is 40uA and M9-M12 of the latch is design in strong inversion and small L in order to inscrease the speed, is it right?
and the M15,M17,M20,M21 of the self-biased amp is design in moderate inversion and small L to decrease the delay time and increase the gain, is it right?
all so, what is the gain from input to output is appropriate, 100db? Is 85db OK? And is the phase magin of the comparator important?


Thank you!
Best regards!
 

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