Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Path based STA is broadly used by current STA sign-off tool (Primetime, TimeCraft). Timing constraints will be checked at endpoint of the timing path.
the AT of endpoint should less than RT.
BLock Based STA:
timing constraints will be checked at each node of the timing path.
each node own its AT and RT. If its AT less than RT, timing is ok.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.