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Regarding timing of a design

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ASIC_intl

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Hi

I have a sunthesized gate level netlist. I want to know the timing information (worst path and some other paths) of this design whose gate level netlist is with me . I may use design compiler for this. Please let meknoe the commands that should be used.
Thanks
ASIC
 

ASIC_intl said:
Hi

I have a sunthesized gate level netlist. I want to know the timing information (worst path and some other paths) of this design whose gate level netlist is with me . I may use design compiler for this. Please let meknoe the commands that should be used.
Thanks
ASIC
Click to expand...

The timing analysis with DC depends on the Operating Conditions, Design Constraints, Wire load model as well as timing strategy you have applied in your HDL design. For the beginner, it'd better that you do your analysis with Design Vision ( the GUI mode of DC ), set the constraint and see the Timing Report.
 

If you have a post-synthesis SDF you can load the design netlist and SDF in Primetime, give appropriate constraints for Clock,IO and exceptions, Set operating conditions and then you can use report_timing to get the timing information
 

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