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LDO design: what should be the nominal DC voltage at gate?

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raduga_in

raduga_in

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LDO design

Here I have a dobut, when you design for the pass element what should be the
nominal DC voltage or Vgs at the gate of the pass element i.e. PMOS in order to
start the design ?

TIA

Raduga
 

LDO design

as high as u can, as u need to minimize the Vgs to assure u r in saturation/subthreshold

Added after 1 minutes:

i mean Vg to be as high (Vgs to be minimum)
 

    raduga_in

    raduga_in

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LDO design

It depends on your LDO loading condition and supply voltage.
 

Re: LDO design

I agree with safwatonline, you need to check with maximum load condition and the output range of your error amplifier.
 

Re: LDO design

maybe DC point is determined by the quiescent current flowing through the feedback resistors.
 

LDO design

depands on your drope voltage
 

Re: LDO design

depends on ur drop out voltage.

if the drop out is less, then Vgs should be less and size of pass transistor is big.implies more pass transistor gate parasitic.
if dropout is less then Vgs should be high, so that size of pass element is small. hence less parasitic gate cap of pass transistor, implies better transient response.
 

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