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jerryzhao said:The top plane has small parasitic capacitor.
1 The parasitic capacitor at input end will decrease the feedback factor, increase the op's bandwidth requirement.
2 top plane far from substrate, they give little niose to OP's input.
jerryzhao said:Why use such a sample/hold in SAR ADC? Did you want to change single input to differential?
If only 5 bit SAR, The comparator can share the S/H op. But the S/H needn't like your architecture.
The ENOB relate to SNDR.
SFDR only the signal power to max tone(Noise or harmonic) ratio.
SNDR is signal to noise and total harmonic distortion ratio.
About comparator: check the speed and resolution and input range, noise, offset.