PLL components interfacing

I am designing a CMOS PLL IC using cadence. The PLL, as we all know, consists of a VCO, a high frequency first divider stage, a series of low frequency dividers followed by a PFD etc.
My question is about the interfacing of the VCO with the first divider stage and
the subsequent divider stages...

1. A buffer is needed after the VCO to avoid frequency pulling etc but do i need a buffer after the first divider stage or not ? What is the best practice in this regard...

2. Let say i want to bias the buffer independently, rather than using the output DC level of the LC-VCO...then i need blocking CAP's at the input of the buffer...How large should these blocking CAPs be?? because caps consume large area...and also the separate biasing will need extra resistors and thus more area...!!

3. If the output DC voltage is good enough from simulations...is it a good idea to connect different components directly and use the output of one to bias the next stage...??

Kindly give your comments and advice on how it is normally done in PLL IC's. I dont see details about such issues in conference or journal papers...

Kind Regards

1 )usually the output of the 1st divider is a CML differential output , so u need some kind of differential to singal ended conversion , usually a high speed OTA can be employed , this also will act as a buffer , if u designed it carefully

2) the caps , will be in the order of RF short circuit , so it don't distort the output singal ,

the DC od the LC VCO if it is PMOS and NMOS pairs about the VDD/2 , which can be used to bias the gate of the buffer

khouly