Analog IP Develeopment- What you will ask for ?

Hi all

I soon will go to an interview as an analog IP developer or , you can call , analog IC designer. I " think " I have a good background on it , but I want to know if YOU will interview me , what type of questions you will ask ?

This will help me much

Thanks in advance

This is one good and innovative way of using the forum.

You should be through with analog design. Concepts of part placements, routing and related issues that could cause problem in the given freq spectrum.
Analog designers more than anything else, rely a lot on their experience and intiution.

All the best.

bimbla.

One think I would ask you is what is the cause of the output resistance of MOS transistors - with good explanation of it, where it comes from, etc. Can you answer?

Following the definition of output “conductance” (from a physical point of view, I like this expression- but no difference) for a MOS transistor; it is (dI/dV).

From which we can see that if the current is constant independent from the applied drain voltage we will have zero conductance (infinite output impedance). This is, to some extent, the case for old long channel MOS with output resistance in the order of M ohm.

But for short channel MOS the I-V characteristics shows an increase in the output current with increasing drain voltage leading to obvious small value for the output resistance.

The increase in the output current with drain voltage (hence the decrease of the output resistance) is due to:
1- Channel Length Modulation (CLM)
2- Drain Induced Barrier Lowering (DIBL) - this decreases the threshold voltage with increased drain voltage leading to additional flow of current.
3- Punch Through - as the channel length decreases, the source & drain depletion regions get very close to each other. This allows the electric field due to drain voltage to draw some electrons thru the depletion region & far from the inversion layer leading to additional current component.

Thanks for your question and waiting more!

a question for you, what's the component of the VCO phase noise, and how would you like to lower the phase noise for a CMOS VCO.

I was asked once.

good answer for CMOS output impedance, inspite of you should have talked about the output impedance in both the triode region and the saturation(active) region.
well buddy, can you tell us why the conversion gain for a double balanced active mixer is 4dB less than the expected value for the same transconductance stage with the same bias current?!
wow, it feels good to be an interviewer

Good. I'm 90% satisfied with your answer about the output impedance of the MOST. But why for example channel length modulation decreases the impedance. And because I antisipate your answer I'd like to ask you to not answer in terms of a formula, but from a more physical point of view. Why the current in saturation increases with higher drain voltages. Assume long channel device.
Second question. If you have an amplifier - opamp or OTA. What would you do to increase the gain and respectively, what would you do to increase the bandwidth? What sets a limit on the increase of the BW, or gain?

The question I would ask you is
(1) how many project of analog IC design you have finished.

(2) Your role in each project.

Well, let us face that questions storm in order!

nozone:

The VCO phase noise components are mainly due to flicker noise and, in principle, internal voltage and current noise sources inside the oscillator loop. These sources inside the loop are amplified thru the oscillator's amplifier and add to the output frequency of the VCO leading to uncertainty in defining zero crossing events in the output waveform compared to one “clean” output. Here I want to remember some words from Asad Abidi I read once : " ... there is no one satisfactory method to predict phase noise in relaxation and ring CMOS oscillators , nor one treatment which unifies and differentiates the mechanisms as how voltage and current noise in the circuit components of an oscillator transform into phase noise"

To lower phase noise in a CMOS VCO there are many things to take care about beginning from floor-planning to circuit topologies used such as:
-You should place the VCO as far as possible from the noisy digital part of your system ( to lower substrate noise effects) & properly guard its control line form any noise as possible.
-Moreover, topology of the counter in the PLL affects the jitter induced thru, say, some clock skew in the counter stages.
-Good design of the current mirrors in the PFD provides "quiet" operation when PLL is locked & reduces the phase noise.
-Good design of PFD to reduce the dead-zone span is required to reduce phase noise degradation from the PLL.
-Using of pseudo differential topologies, with some care, reduces the current-induced noise, lowers the circuit head-room & increases the output swing.

godz:

I think the cause for output impedance in the triode region is obvious as the current and drain voltage are related to each other in a direct linear relation, if the drain voltage is lower enough than the overdrive voltage. Thus, I don’t talk about it.

As to the tricky question you posted about conversion gain for both double balanced active mixer and the transconductance stage - RIGTH NOW, I don't have a clear answer. It seems to me I need to do some investigation about that! (I like this type of questions - but not in an interview!)

sutapanaki:

At the onset of the saturation, the channel in pinched off at the drain. With higher drain voltages, the pinch-off point is moving toward the source keeping its potential at the same value of the saturation voltage. In long channel case, without any effect to lower the threshold voltage, the difference between the applied voltage and the saturation voltage is applied on the region between the drain end and the pinch-off point leading to higher electric field that draw more electrons , or it draws them at higher speed , from the channel to the drain end and hence increasing the drain current. Actually, these electrons flow away from the surface & its analysis required some 2D electric field solution. I hope I got what you want me to answer.

About the second question, I want to know if you are asking me to increase the gain and then increase the bandwidth at the same time or just how to increase them separately. I think the limitation on increasing the bandwidth and gain is the stability of the amplifier and the required performance factors like, for example, slew rate.

my_design:

Thanks for your questions, but the type of questions meant is of technical type and not related to the experience or previous work as this should already be known to the interviewer in advance.

Many thanks for all of you. Waiting for more!

Again good answers. There is just one slight thing that I don't quite agree with:
"...leading to higher electric field that draw more electrons , or it draws them at higher speed , from the channel to the drain end and hence increasing the drain current."
I don't think the depletion region field draws more electrons at a higher speed. To me the speed there is either saturated or is the speed at which the electrons leave the pinched-off channel. This is because the source of electrons is actually the channel - like a waterfall whose through-put is defined by the amount of water there is just before (at the edge of) the waterfall. To me the output impedance comes from the reducton of the effective length of the remaining part of the channel - the smae voltage Vdsat at a shorter length, should mean higher speed (if not saturated) for the same amount of charge (defined by Vgs-Vt).
For the gain and BW - well, let's split it in 3 parts: increase/decrease the gain alone; increase the BW alone; What would you do if you want more gain at higher BW or want more BW for the same gain.
And once you mentioned slew-rate, here is one more: usually slew-rate limitation is said to come from the Miller capacitor (when you use this kind of compensation). Let's say the load/output capacitance is comparable in size to the Miller (not the efffective Miller) capacitance. How would the output capacitance influence the SR?