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issues about test patterns generation for ATE

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ls000rhb

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my recent responsibility is to generate test patterns for ATE. The DUT is a mixed-signal chip. But i am a new in this domain. would all of you pls give me some suggestions on procedures and common tools.

Thanks in advance


BR.
ls000rhb[/i]
 

For digital patterns, most people use a simulator (Verilog, VHDL), in conjunction with a vector translation tool (TSSI, VTRAN, etc) that will convert the simulation output to the ATE format.

For analog functions, there usually is not much in the way of patterns to generate, unless there are register settings to be programmed.

John

for DFT talk/info, go to:
DFT Digest
DFT Forum
 

DFT Forum is usefully
 

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