Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
In the analog layout design, how to design the size of biploar. the foundry only supply the size of emiter,but how to fix on the size of collector and base.
Are you talking about a parasitc vertical pnp transistor???
If so, for a 10ux10u emitter area you should use a 16ux16u base area
for 5ux5u emitter, a 11ux11u base
for 2ux2u emitter, 8ux8u base
(6u longer on each dimension)
The collector would be the whole P-Substrate for an n-well process, but you wold like to use a subite ring (like about 22ux22u for a 10ux10u emitter transistor)
You can increase size of base and collector but will not profit from it.
Look at the crosssection of the device architecture and you will see why.
Area of emitter is then the only parameter which makes sense to change.
so if the foundry supply me the emitter size and its spice model, like 16*20um for example, I could only use this fixed size, and could not change it. so that all the bipolar in my circuit have the same size?
Emitter size decide ur current ability
other size decide the Voltage can support. anysize you can use ,if the rule is correct. usually stand cell alse be used.
I think
best regard!
Foundry only supplies fixed size emitter area of the bipolar transistor. They provide the spice model of that standard device. So you need to increase the emitter area due to current capabilities, you need to parallel the transistors to get larger emitte size. The disadvantage is it will be interm of multiples (discrete).
You can not change the emitter because you will not have models and it is not characterised.
I have some understand. but as you have explained, I could only increase the current capacities discretely, not continue. so that may not be convenient to the circuit design.
Yes, you are right. In bipolar technologies, you can only do that. Just choose the highest near discrete number, you should meet your requirements on current capabilities. It is ok to over design.
It is not the same for MOS technologies which you have w and l to play with.
Bipolar has its advantages over cmos. It depends on what your design and your circuit requirments.
Usually the would give the model for 2 or 3 different sized BJT so that you have more variety. But if you need a different size beside those you would have to use the discrete aproach.
Hello
I know that foundry provide pnp model+predifined layout cell.
If You propose self pnp layout, provided model can predict it dc performance
inaccurate
This is important if You are design bandgap ref (for ex)
Regards
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
